Week 03: FIR and Other Things
Accelerators
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Overview
In this week/lab/whatever you'll be creating a simple, pipelined FIR filter, build some code to test it against some "gold-standard" scipy models of FIR filters, and then finally deploy it into video pipeline on the Pynq board. I think the Vivado project this week is going to be a bit hairier than ones in the past so start early on it, if possible (we'll see...maybe it will be fine).
After this week, you'll have been exposed to most pieces of IP and other things in the Xilinx ecosystem. Next week we'll look at Direct Memory Access, and then after that we'll move onto the RFSoC boards.
Individual Parts
- (SV, Cocotb): FIR Design
- (Pynq, Vivado, FPGA): Pynq Integration