Catalog Description

updated for Fall 2025: 6.S965 is a continuation of topics introduced in Digital Systems Laboratory (6.205). There will be a particular focus on modern design verification practices, System Verilog, and Cocotb, as well as designing complex digital systems in hybrid platforms including Xilinx SoC and RFSoC devices. Weekly assignments involving both homework and lab work and final design project with emphasis on signal processing, RF, data acquisition, and other applications. The course will utilize a number of tools and areas of study in pursuit of our work, reflective of the hybrid modern state of the field, so usage of C, Python, shells scripts, signals and systems, communications, and RF concepts, should be expected.

Prerequisites

The prerequisite for class is 6.205.

Units

2-8-2

Lectures/Recitations

Monday, Wednesday 3:30-5:00pm in 36-112. I do not believe we will record class.

Lab Space

The lab room is the left (southern) portion of building 38's 6th floor. Office hours will take place here. You can work at any lab benches, though will likely want to work at ones with the SoC systems. All machines should be log-in-able. Your user name is your kerberos. Your password is your MIT ID number. Obviously this is not RSA-level secure so don't put sensitive information on the machines. The machines are not synchronized. Saving a file on one will not put it onto another. It is your job to maintain move files around (git, usb stick, whatever).

Lab Kit

Lab kits are likely not going to be take-home-able for the first half of the class. The SoCs need routers set up for the Pynq framework to work, I don't have enough of the SOCs, and the RFSoCs are too expensive for them to leave lab. Portions of work every week can definitely be done on your own computer, but the lab portions will likely need you to be in lab at least for a bit.

Piazza

The class piazza will be used for all important announcements as well as our official help forum for the class. It is your responsibility to make sure to join it and to set their email up so they see these announcements in a timely manner.

Textbook

We'll use several textbooks for readings and things. One of them is the following:

• Software Defined Radio with Zynq Ultrascale+ RFSoC by Crocket et al
• The Zynq Book by Crocket et al
• FPGA-based Implementation of Signal Processing Systems by Woods et al

Others will be provided as needed. No book needs to get bought in this class.

Staff

Show/Hide:
Instructors
TAs
LAs

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Joe
Steinmeyer

Instructor
jodalyst@mit.edu

38-583

Oliver
Trevor

TA
olt@mit.edu

 
 

Grading

Your overall grade is based on the following breakdown:

• Approximately Eight Weekly Assignments: 50%
• Final Project: 50% (Including the technical and communication components of abstract, proposal, revisions, meetings, and final report)

This is a grad class and the second time we're offering it. I expect grading to be relatively generous, though I'm totally down to dance if you want to take advantage of that and not put in effort. Since we're still in "development mode" with our S-prefixed course number, satisfactory performance in the class will also entail providing feedback and helping us figure out and evolve this class into something useful.

Weekly Assignments

Every week after class on Friday, the upcoming week's assignments will be released. They will be due the following Friday at 5:00pm Boston time. The assignment for the week is comprised of a number of chunks, specifically:

• Exercises: Maybe some theory, maybe some code (Python/cocotb/simulations), maybe some other non-lab stuff
• Labs: A set of tasks you complete using the lab equipment.

We expect to have about seven weeks of assignments for Fall 2025 before we start final projects. See the calendar for particular dates of when they are released and when they are due, but it will largely be a Thursday-to-Wednesday pattern. You are to work on these assignments in your own time (there are no "lab" sessions), though you should feel free to come to office hours and utilize Piazza.

The assignments will be uploaded when completed by their due date and then I will grade them in a somewhat reasonable timeframe.

Final Project

Collectively this makes up approximately 50% of your grade. There will be more details as we get closer to final projects

(No) Exams

There will be no exams in 6.S965. You are welcome.

Late Submissions

Work is due when it is due. There are no slack days or linear point decays or anything like that. Just get it in on time. If you need to submit work late, please reach out to me >24 hours prior and we can discuss options. Do not abuse this. My response to requests for extensions will be stateful, taking into account past requests from you.

Collaboration and Work that is Not Your Own

To make it short and simple: Everything in this class should be your own work. You can work together, of course, at a high level, but do not copy someone else's work. This includes using some online tool that generates answers for you. Do not email working code to "help" one another. Do not submit somebody else's code. Do not use "your" "friend"'s module because it works and is easier or you're tired. Do not vibe code. You're here to learn. What a waste of everybody's time if you're not trying to do that. Your work should be your own. You should not use tools like ChatGPT when creating code or reports or presentations. Your work needs to be your own. The point of you doing assignments is to improve yourself. The point is not to provide me with a working design. If I just wanted to get a working design, I would do it myself and not ask you to do it. If we catch you, it will result in a grade of zero on the assignment, and it will be reported to the Committee on Discipline (COD). Just don't do it.