Coverage
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Design and Build a Skid Buffer
In lecture 12, we talked about coverage. We went through the cocotb coverage library (install version 1.2!) and then we walked through some basic coverage structure on the skid buffer. The code mostly as I left it off without the Drivers included (since you've already written that) can be found here.
If you run this test code on your skid buffer from last week, hopefully it passes, but more relevant to the discussion at hand is how much did you actually "cover" in testing. In lecture I basically left off with the question are we fully covering the AXIS transaction space (at least as it is concerned with valid and ready signals toggling) on each AXIS port. If you run it, you'll likely get a coverage report back that looks something similar to this.
top.os.m_cross : <cocotb_coverage.coverage.CoverCross object at 0x107f45f90>, coverage=12, size=16
BIN ('V:0->0', 'R:0->0') : 14
BIN ('V:0->0', 'R:0->1') : 4
BIN ('V:0->0', 'R:1->0') : 0
BIN ('V:0->0', 'R:1->1') : 154
BIN ('V:0->1', 'R:0->0') : 5
BIN ('V:0->1', 'R:0->1') : 1
BIN ('V:0->1', 'R:1->0') : 0
BIN ('V:0->1', 'R:1->1') : 43
BIN ('V:1->0', 'R:0->0') : 0
BIN ('V:1->0', 'R:0->1') : 0
BIN ('V:1->0', 'R:1->0') : 9
BIN ('V:1->0', 'R:1->1') : 40
BIN ('V:1->1', 'R:0->0') : 110
BIN ('V:1->1', 'R:0->1') : 20
BIN ('V:1->1', 'R:1->0') : 15
BIN ('V:1->1', 'R:1->1') : 86
top.os.s00_tready : <cocotb_coverage.coverage.CoverPoint object at 0x107f45d10>, coverage=4, size=4
BIN R:0->0 : 88
BIN R:0->1 : 16
BIN R:1->0 : 16
BIN R:1->1 : 381
top.os.s00_tvalid : <cocotb_coverage.coverage.CoverPoint object at 0x107ad27b0>, coverage=4, size=4
BIN V:0->0 : 199
BIN V:0->1 : 51
BIN V:1->0 : 51
BIN V:1->1 : 200
top.os.s_cross : <cocotb_coverage.coverage.CoverCross object at 0x107ad2a50>, coverage=10, size=16
BIN ('V:0->0', 'R:0->0') : 1
BIN ('V:0->0', 'R:0->1') : 2
BIN ('V:0->0', 'R:1->0') : 0
BIN ('V:0->0', 'R:1->1') : 196
BIN ('V:0->1', 'R:0->0') : 0
BIN ('V:0->1', 'R:0->1') : 0
BIN ('V:0->1', 'R:1->0') : 0
BIN ('V:0->1', 'R:1->1') : 51
BIN ('V:1->0', 'R:0->0') : 0
BIN ('V:1->0', 'R:0->1') : 0
BIN ('V:1->0', 'R:1->0') : 2
BIN ('V:1->0', 'R:1->1') : 49
BIN ('V:1->1', 'R:0->0') : 87
BIN ('V:1->1', 'R:0->1') : 14
BIN ('V:1->1', 'R:1->0') : 14
BIN ('V:1->1', 'R:1->1') : 85
As discussed towards the end of lecture, some of these patterns probably shouldn't be things we care about testing (they are out of AXI spec). Others are related to patterns that perhaps should not be showing up from the DUT (for actual justified reasons). Others, should be getting showing up and currently aren't being tested.
For this assignment, update this code so that both the s_cross and m_cross coverages are 100%. Achieve this by either ignoring certain cases in the two Cover crosses (and I emphasize: justifiably ignoring NOT just ignoring everything to get to 100% like people did overwriting count in what I thought would be an intellectually stimulating cocotb adventure with the Verilog simulation engine in week 2, never again.) For every element in the cross you ignore, add a comment explaining why. For things that should not be getting ignored, update your testbench (and possibly expand out your drivers) to get all the needed behavior for full coverage!
When done, upload:
