{ "cells": [ { "cell_type": "code", "execution_count": 4, "id": "f645cb2f", "metadata": {}, "outputs": [ { "name": "stdout", "output_type": "stream", "text": [ "{'real_dma': {'addr_range': 65536,\n", " 'bdtype': None,\n", " 'device': ,\n", " 'driver': ,\n", " 'fullpath': 'real_dma',\n", " 'gpio': {},\n", " 'interrupts': {},\n", " 'mem_id': 'S_AXI_LITE',\n", " 'memtype': 'REGISTER',\n", " 'parameters': {'ADDR_WIDTH': '10',\n", " 'ARUSER_WIDTH': '0',\n", " 'AWUSER_WIDTH': '0',\n", " 'BUSER_WIDTH': '0',\n", " 'CLK_DOMAIN': 'design_1_zynq_ultra_ps_e_0_0_pl_clk0',\n", " 'C_BASEADDR': '0xA0000000',\n", " 'C_DLYTMR_RESOLUTION': '125',\n", " 'C_ENABLE_MULTI_CHANNEL': '0',\n", " 'C_FAMILY': 'zynquplus',\n", " 'C_HIGHADDR': '0xA000FFFF',\n", " 'C_INCLUDE_MM2S': '0',\n", " 'C_INCLUDE_MM2S_DRE': '0',\n", " 'C_INCLUDE_MM2S_SF': '1',\n", " 'C_INCLUDE_S2MM': '1',\n", " 'C_INCLUDE_S2MM_DRE': '0',\n", " 'C_INCLUDE_S2MM_SF': '1',\n", " 'C_INCLUDE_SG': '0',\n", " 'C_INCREASE_THROUGHPUT': '0',\n", " 'C_MICRO_DMA': '0',\n", " 'C_MM2S_BURST_SIZE': '16',\n", " 'C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH': '32',\n", " 'C_M_AXIS_MM2S_TDATA_WIDTH': '32',\n", " 'C_M_AXI_MM2S_ADDR_WIDTH': '32',\n", " 'C_M_AXI_MM2S_DATA_WIDTH': '32',\n", " 'C_M_AXI_S2MM_ADDR_WIDTH': '32',\n", " 'C_M_AXI_S2MM_DATA_WIDTH': '128',\n", " 'C_M_AXI_SG_ADDR_WIDTH': '32',\n", " 'C_M_AXI_SG_DATA_WIDTH': '32',\n", " 'C_NUM_MM2S_CHANNELS': '1',\n", " 'C_NUM_S2MM_CHANNELS': '1',\n", " 'C_PRMRY_IS_ACLK_ASYNC': '0',\n", " 'C_S2MM_BURST_SIZE': '16',\n", " 'C_SG_INCLUDE_STSCNTRL_STRM': '0',\n", " 'C_SG_LENGTH_WIDTH': '23',\n", " 'C_SG_USE_STSAPP_LENGTH': '0',\n", " 'C_S_AXIS_S2MM_STS_TDATA_WIDTH': '32',\n", " 'C_S_AXIS_S2MM_TDATA_WIDTH': '128',\n", " 'C_S_AXI_LITE_ADDR_WIDTH': '10',\n", " 'C_S_AXI_LITE_DATA_WIDTH': '32',\n", " 'Component_Name': 'design_1_axi_dma_0_0',\n", " 'DATA_WIDTH': '32',\n", " 'EDK_IPTYPE': 'PERIPHERAL',\n", " 'FREQ_HZ': '149999969',\n", " 'HAS_BRESP': '1',\n", " 'HAS_BURST': '0',\n", " 'HAS_CACHE': '0',\n", " 'HAS_LOCK': '0',\n", " 'HAS_PROT': '0',\n", " 'HAS_QOS': '0',\n", " 'HAS_REGION': '0',\n", " 'HAS_RRESP': '1',\n", " 'HAS_TKEEP': '1',\n", " 'HAS_TLAST': '1',\n", " 'HAS_TREADY': '1',\n", " 'HAS_TSTRB': '0',\n", " 'HAS_WSTRB': '0',\n", " 'ID_WIDTH': '0',\n", " 'INSERT_VIP': '0',\n", " 'LAYERED_METADATA': 'undef',\n", " 'MAX_BURST_LENGTH': '1',\n", " 'NUM_READ_OUTSTANDING': '8',\n", " 'NUM_READ_THREADS': '1',\n", " 'NUM_WRITE_OUTSTANDING': '8',\n", " 'NUM_WRITE_THREADS': '1',\n", " 'PHASE': '0.0',\n", " 'PROTOCOL': 'AXI4LITE',\n", " 'READ_WRITE_MODE': 'READ_WRITE',\n", " 'RUSER_BITS_PER_BYTE': '0',\n", " 'RUSER_WIDTH': '0',\n", " 'SUPPORTS_NARROW_BURST': '0',\n", " 'TDATA_NUM_BYTES': '16',\n", " 'TDEST_WIDTH': '0',\n", " 'TID_WIDTH': '0',\n", " 'TUSER_WIDTH': '0',\n", " 'WUSER_BITS_PER_BYTE': '0',\n", " 'WUSER_WIDTH': '0',\n", " 'c_addr_width': '32',\n", " 'c_dlytmr_resolution': '125',\n", " 'c_enable_multi_channel': '0',\n", " 'c_include_mm2s': '0',\n", " 'c_include_mm2s_dre': '0',\n", " 'c_include_mm2s_sf': '1',\n", " 'c_include_s2mm': '1',\n", " 'c_include_s2mm_dre': '0',\n", " 'c_include_s2mm_sf': '1',\n", " 'c_include_sg': '0',\n", " 'c_increase_throughput': '0',\n", " 'c_m_axi_mm2s_data_width': '32',\n", " 'c_m_axi_s2mm_data_width': '128',\n", " 'c_m_axis_mm2s_tdata_width': '32',\n", " 'c_micro_dma': '0',\n", " 'c_mm2s_burst_size': '16',\n", " 'c_num_mm2s_channels': '1',\n", " 'c_num_s2mm_channels': '1',\n", " 'c_prmry_is_aclk_async': '0',\n", " 'c_s2mm_burst_size': '16',\n", " 'c_s_axis_s2mm_tdata_width': '128',\n", " 'c_sg_include_stscntrl_strm': '0',\n", " 'c_sg_length_width': '23',\n", " 'c_sg_use_stsapp_length': '0',\n", " 'c_single_interface': '0'},\n", " 'phys_addr': 2684354560,\n", " 'registers': {'MM2S_CURDESC': {'access': 'read-write',\n", " 'address_offset': 8,\n", " 'description': 'MM2S DMA Current '\n", " 'Descriptor '\n", " 'Pointer Register',\n", " 'fields': {'Current_Descriptor_Pointer': {'access': 'read-write',\n", " 'bit_offset': 6,\n", " 'bit_width': 26,\n", " 'description': 'Indicates '\n", " 'the '\n", " 'pointer '\n", " 'of '\n", " 'the '\n", " 'current '\n", " 'descriptor '\n", " 'being '\n", " 'worked '\n", " 'on. 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'\n", " 'AXI4-Stream '\n", " 'outs '\n", " 'are '\n", " 'potentially '\n", " 'terminated.\\n'\n", " ' '\n", " 'The '\n", " 'halted '\n", " 'bit '\n", " 'in '\n", " 'the '\n", " 'DMA '\n", " 'Status '\n", " 'register '\n", " 'asserts '\n", " 'to '\n", " '1 '\n", " 'when '\n", " 'the '\n", " 'DMA '\n", " 'engine '\n", " 'is '\n", " 'halted. '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'cleared '\n", " 'by '\n", " 'AXI '\n", " 'DMA '\n", " 'hardware '\n", " 'when '\n", " 'an '\n", " 'error '\n", " 'occurs. '\n", " 'The '\n", " 'CPU '\n", " 'can '\n", " 'also '\n", " 'choose '\n", " 'to '\n", " 'clear '\n", " 'this '\n", " 'bit '\n", " 'to '\n", " 'stop '\n", " 'DMA '\n", " 'operations.\\n'\n", " ' '\n", " '1 '\n", " '- '\n", " 'Run, '\n", " 'Start '\n", " 'DMA '\n", " 'operations. '\n", " 'The '\n", " 'halted '\n", " 'bit '\n", " 'in '\n", " 'the '\n", " 'DMA '\n", " 'Status '\n", " 'register '\n", " 'deasserts '\n", " 'to '\n", " '0 '\n", " 'when '\n", " 'the '\n", " 'DMA '\n", " 'engine '\n", " 'begins '\n", " 'operations.\\n'},\n", " 'Reset': {'access': 'read-write',\n", " 'bit_offset': 2,\n", " 'bit_width': 1,\n", " 'description': 'Soft '\n", " 'reset '\n", " 'for '\n", " 'resetting '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'core. '\n", " 'Setting '\n", " 'this '\n", " 'bit '\n", " 'to '\n", " 'a '\n", " '1 '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'be '\n", " 'reset. '\n", " 'Reset '\n", " 'is '\n", " 'accomplished '\n", " 'gracefully. '\n", " 'Pending '\n", " 'commands/transfers '\n", " 'are '\n", " 'flushed '\n", " 'or '\n", " 'completed.\\n'\n", " 'AXI4-Stream '\n", " 'outs '\n", " 'are '\n", " 'potentially '\n", " 'terminated '\n", " 'early. '\n", " 'Setting '\n", " 'either '\n", " 'MM2S_DMACR. '\n", " 'Reset '\n", " '= '\n", " '1 '\n", " 'or '\n", " 'S2MM_DMACR.Reset '\n", " '= '\n", " '1 '\n", " 'resets '\n", " 'the '\n", " 'entire '\n", " 'AXI '\n", " 'DMA '\n", " 'engine. '\n", " 'After '\n", " 'completion '\n", " 'of '\n", " 'a '\n", " 'soft '\n", " 'reset, '\n", " 'all '\n", " 'registers '\n", " 'and '\n", " 'bits '\n", " 'are '\n", " 'in '\n", " 'the '\n", " 'Reset '\n", " 'State. '\n", " '0 '\n", " '- '\n", " 'Normal '\n", " 'operation. '\n", " '1 '\n", " '- '\n", " 'Reset '\n", " 'in '\n", " 'progress.\\n'}},\n", " 'size': 32},\n", " 'MM2S_DMASR': {'access': 'read-write',\n", " 'address_offset': 4,\n", " 'description': 'MM2S DMA Status '\n", " 'Register',\n", " 'fields': {'DMADecErr': {'access': 'read-only',\n", " 'bit_offset': 6,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Decode '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'address '\n", " 'request '\n", " 'points '\n", " 'to '\n", " 'an '\n", " 'invalid '\n", " 'address. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'DMA '\n", " 'Decode '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'Decode '\n", " 'Error '\n", " 'detected. '\n", " 'DMA '\n", " 'Engine '\n", " 'halts.\\n'},\n", " 'DMAIntErr': {'access': 'read-only',\n", " 'bit_offset': 4,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Internal '\n", " 'Error. '\n", " 'Internal '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'buffer '\n", " 'length '\n", " 'specified '\n", " 'in '\n", " 'the '\n", " 'fetched '\n", " 'descriptor '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'DMA '\n", " 'Internal '\n", " 'Errors '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'Internal '\n", " 'Error '\n", " 'detected. '\n", " 'DMA '\n", " 'Engine '\n", " 'halts\\n'},\n", " 'DMASlvErr': {'access': 'read-only',\n", " 'bit_offset': 5,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Slave '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'slave '\n", " 'read '\n", " 'from '\n", " 'the '\n", " 'Memory '\n", " 'Map '\n", " 'interface '\n", " 'issues '\n", " 'a '\n", " 'Slave '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'DMA '\n", " 'Slave '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'Slave '\n", " 'Error '\n", " 'detected. '\n", " 'DMA '\n", " 'Engine '\n", " 'halts\\n'},\n", " 'Dly_Irq': {'access': 'read-write',\n", " 'bit_offset': 13,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Delay. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'indicates '\n", " 'an '\n", " 'interrupt '\n", " 'event '\n", " 'was '\n", " 'generated '\n", " 'on '\n", " 'delay '\n", " 'timer '\n", " 'time '\n", " 'out. '\n", " 'If '\n", " 'the '\n", " 'corresponding '\n", " 'bit '\n", " 'is '\n", " 'enabled '\n", " 'in '\n", " 'the '\n", " 'MM2S_DMACR '\n", " '(Dly_IrqEn '\n", " '= '\n", " '1), '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'is '\n", " 'generated '\n", " 'from '\n", " 'the '\n", " 'AXI '\n", " 'DMA. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'Delay '\n", " 'Interrupt. '\n", " '1 '\n", " '- '\n", " 'Delay '\n", " 'Interrupt '\n", " 'detected. '\n", " 'Note: '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'not '\n", " 'used '\n", " 'and '\n", " 'is '\n", " 'fixed '\n", " 'at '\n", " '0 '\n", " 'when '\n", " 'AXI '\n", " 'DMA '\n", " 'is '\n", " 'configured '\n", " 'for '\n", " 'Direct '\n", " 'Register '\n", " 'Mode. \\n'},\n", " 'Err_Irq': {'access': 'read-write',\n", " 'bit_offset': 14,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Error. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'indicates '\n", " 'an '\n", " 'interrupt '\n", " 'event '\n", " 'was '\n", " 'generated '\n", " 'on '\n", " 'error. '\n", " 'If '\n", " 'the '\n", " 'corresponding '\n", " 'bit '\n", " 'is '\n", " 'enabled '\n", " 'in '\n", " 'the '\n", " 'MM2S_DMACR '\n", " '(Err_IrqEn '\n", " '= '\n", " '1), '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'is '\n", " 'generated '\n", " 'from '\n", " 'the '\n", " 'AXI '\n", " 'DMA.\\n'\n", " 'Writing '\n", " 'a '\n", " '1 '\n", " 'to '\n", " 'this '\n", " 'bit '\n", " 'will '\n", " 'clear '\n", " 'it. \\n'\n", " '0 '\n", " '- '\n", " 'No '\n", " 'error '\n", " 'Interrupt. \\n'\n", " '1 '\n", " '- '\n", " 'Error '\n", " 'interrupt '\n", " 'detected.\\n'},\n", " 'Halted': {'access': 'read-only',\n", " 'bit_offset': 0,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Channel '\n", " 'Halted. '\n", " 'Indicates '\n", " 'the '\n", " 'run/stop '\n", " 'state '\n", " 'of '\n", " 'the '\n", " 'DMA '\n", " 'channel. '\n", " '0 '\n", " '- '\n", " 'DMA '\n", " 'channel '\n", " 'running. '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'channel '\n", " 'halted. '\n", " 'For '\n", " 'Scatter '\n", " '/ '\n", " 'Gather '\n", " 'Mode '\n", " 'this '\n", " 'bit '\n", " 'gets '\n", " 'set '\n", " 'when '\n", " 'DMACR.RS '\n", " '= '\n", " '0 '\n", " 'and '\n", " 'DMA '\n", " 'and '\n", " 'SG '\n", " 'operations '\n", " 'have '\n", " 'halted. '\n", " 'For '\n", " 'Direct '\n", " 'Register '\n", " 'mode '\n", " '(C_INCLUDE_SG '\n", " '= '\n", " '0) '\n", " 'this '\n", " 'bit '\n", " 'gets '\n", " 'set '\n", " 'when '\n", " 'DMACR.RS '\n", " '= '\n", " '0 '\n", " 'and '\n", " 'DMA '\n", " 'operations '\n", " 'have '\n", " 'halted. '\n", " 'There '\n", " 'can '\n", " 'be '\n", " 'a '\n", " 'lag '\n", " 'of '\n", " 'time '\n", " 'between '\n", " 'when '\n", " 'DMACR.RS '\n", " '= '\n", " '0 '\n", " 'and '\n", " 'when '\n", " 'DMASR.Halted '\n", " '= '\n", " '1 '\n", " 'Note: '\n", " 'When '\n", " 'halted '\n", " '(RS= '\n", " '0 '\n", " 'and '\n", " 'Halted '\n", " '= '\n", " '1), '\n", " 'writing '\n", " 'to '\n", " 'CURDESC_PTR '\n", " 'or '\n", " 'TAILDESC_PTR '\n", " 'pointer '\n", " 'registers '\n", " 'has '\n", " 'no '\n", " 'effect '\n", " 'on '\n", " 'DMA '\n", " 'operations '\n", " 'when '\n", " 'in '\n", " 'Scatter '\n", " 'Gather '\n", " 'Mode. '\n", " 'For '\n", " 'Direct '\n", " 'Register '\n", " 'Mode, '\n", " 'writing '\n", " 'to '\n", " 'the '\n", " 'LENGTH '\n", " 'register '\n", " 'has '\n", " 'no '\n", " 'effect '\n", " 'on '\n", " 'DMA '\n", " 'operations.\\n'},\n", " 'IOC_Irq': {'access': 'read-write',\n", " 'bit_offset': 12,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Complete. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1 '\n", " 'for '\n", " 'Scatter/Gather '\n", " 'Mode, '\n", " 'indicates '\n", " 'an '\n", " 'interrupt '\n", " 'event '\n", " 'was '\n", " 'generated '\n", " 'on '\n", " 'completion '\n", " 'of '\n", " 'a '\n", " 'descriptor. '\n", " 'This '\n", " 'occurs '\n", " 'for '\n", " 'descriptors '\n", " 'with '\n", " 'the '\n", " 'End '\n", " 'of '\n", " 'Frame '\n", " '(EOF) '\n", " 'bit '\n", " 'set. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1 '\n", " 'for '\n", " 'Direct '\n", " 'Register '\n", " 'Mode, '\n", " 'indicates '\n", " 'an '\n", " 'interrupt '\n", " 'event '\n", " 'was '\n", " 'generated '\n", " 'on '\n", " 'completion '\n", " 'of '\n", " 'a '\n", " 'transfer. '\n", " 'If '\n", " 'the '\n", " 'corresponding '\n", " 'bit '\n", " 'is '\n", " 'enabled '\n", " 'in '\n", " 'the '\n", " 'MM2S_DMACR '\n", " '(IOC_IrqEn '\n", " '= '\n", " '1) '\n", " 'and '\n", " 'if '\n", " 'the '\n", " 'interrupt '\n", " 'threshold '\n", " 'has '\n", " 'been '\n", " 'met, '\n", " 'causes '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'to '\n", " 'be '\n", " 'generated '\n", " 'from '\n", " 'the '\n", " 'AXI '\n", " 'DMA. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'IOC '\n", " 'Interrupt. '\n", " '1 '\n", " '- '\n", " 'IOC '\n", " 'Interrupt '\n", " 'detected. '\n", " 'Writing '\n", " 'a '\n", " '1 '\n", " 'to '\n", " 'this '\n", " 'bit '\n", " 'will '\n", " 'clear '\n", " 'it.\\n'},\n", " 'IRQDelaySts': {'access': 'read-only',\n", " 'bit_offset': 24,\n", " 'bit_width': 8,\n", " 'description': 'Interrupt '\n", " 'Delay '\n", " 'Time '\n", " 'Status. '\n", " 'Indicates '\n", " 'current '\n", " 'interrupt '\n", " 'delay '\n", " 'time '\n", " 'value.\\n'\n", " 'Note: '\n", " 'Applicable '\n", " 'only '\n", " 'when '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'enabled.\\n'},\n", " 'IRQThresholdSts': {'access': 'read-only',\n", " 'bit_offset': 16,\n", " 'bit_width': 8,\n", " 'description': 'Interrupt '\n", " 'Threshold '\n", " 'Status. '\n", " 'Indicates '\n", " 'current '\n", " 'interrupt '\n", " 'threshold '\n", " 'value.\\n'\n", " 'Note: '\n", " 'Applicable '\n", " 'only '\n", " 'when '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'enabled.\\n'},\n", " 'Idle': {'access': 'read-only',\n", " 'bit_offset': 1,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Channel '\n", " 'Idle. '\n", " 'Indicates '\n", " 'the '\n", " 'state '\n", " 'of '\n", " 'AXI '\n", " 'DMA '\n", " 'operations.\\n'\n", " 'For '\n", " 'Scatter '\n", " '/ '\n", " 'Gather '\n", " 'Mode '\n", " 'when '\n", " 'IDLE '\n", " 'indicates '\n", " 'the '\n", " 'SG '\n", " 'Engine '\n", " 'has '\n", " 'reached '\n", " 'the '\n", " 'tail '\n", " 'pointer '\n", " 'for '\n", " 'the '\n", " 'associated '\n", " 'channel '\n", " 'and '\n", " 'all '\n", " 'queued '\n", " 'descriptors '\n", " 'have '\n", " 'been '\n", " 'processed. '\n", " 'Writing '\n", " 'to '\n", " 'the '\n", " 'tail '\n", " 'pointer '\n", " 'register '\n", " 'automatically '\n", " 'restarts '\n", " 'DMA '\n", " 'operations.\\n'\n", " 'For '\n", " 'Direct '\n", " 'Register '\n", " 'Mode '\n", " 'when '\n", " 'IDLE '\n", " 'indicates '\n", " 'the '\n", " 'current '\n", " 'transfer '\n", " 'has '\n", " 'completed. '\n", " '0 '\n", " '- '\n", " 'Not '\n", " 'Idle. '\n", " 'For '\n", " 'Scatter '\n", " '/ '\n", " 'Gather '\n", " 'Mode, '\n", " 'SG '\n", " 'has '\n", " 'not '\n", " 'reached '\n", " 'tail '\n", " 'descriptor '\n", " 'pointer '\n", " 'and/or '\n", " 'DMA '\n", " 'operations '\n", " 'in '\n", " 'progress. '\n", " 'For '\n", " 'Direct '\n", " 'Register '\n", " 'Mode, '\n", " 'transfer '\n", " 'is '\n", " 'not '\n", " 'complete. '\n", " '1 '\n", " '- '\n", " 'Idle. '\n", " 'For '\n", " 'Scatter '\n", " '/ '\n", " 'Gather '\n", " 'Mode, '\n", " 'SG '\n", " 'has '\n", " 'reached '\n", " 'tail '\n", " 'descriptor '\n", " 'pointer '\n", " 'and '\n", " 'DMA '\n", " 'operation '\n", " 'paused. '\n", " 'for '\n", " 'Direct '\n", " 'Register '\n", " 'Mode, '\n", " 'DMA '\n", " 'transfer '\n", " 'has '\n", " 'completed '\n", " 'and '\n", " 'controller '\n", " 'is '\n", " 'paused. '\n", " 'Note: '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " '0 '\n", " 'when '\n", " 'channel '\n", " 'is '\n", " 'halted '\n", " '(DMASR.Halted=1). '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'also '\n", " '0 '\n", " 'prior '\n", " 'to '\n", " 'initial '\n", " 'transfer '\n", " 'when '\n", " 'AXI '\n", " 'DMA '\n", " 'configured '\n", " 'for '\n", " 'Direct '\n", " 'Register '\n", " 'Mode.\\n'},\n", " 'SGDecErr': {'access': 'read-only',\n", " 'bit_offset': 10,\n", " 'bit_width': 1,\n", " 'description': 'Scatter '\n", " 'Gather '\n", " 'Decode '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'CURDESC_PTR '\n", " 'and/or '\n", " 'NXTDESC_PTR '\n", " 'points '\n", " 'to '\n", " 'an '\n", " 'invalid '\n", " 'address. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'SG '\n", " 'Decode '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'SG '\n", " 'Decode '\n", " 'Error '\n", " 'detected. '\n", " 'DMA '\n", " 'Engine '\n", " 'halts. '\n", " 'Note: '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'not '\n", " 'used '\n", " 'and '\n", " 'is '\n", " 'fixed '\n", " 'at '\n", " '0 '\n", " 'when '\n", " 'AXI '\n", " 'DMA '\n", " 'is '\n", " 'configured '\n", " 'for '\n", " 'Direct '\n", " 'Register '\n", " 'Mode. \\n'},\n", " 'SGIncld': {'access': 'read-only',\n", " 'bit_offset': 3,\n", " 'bit_width': 1,\n", " 'description': '1 '\n", " '- '\n", " 'Scatter '\n", " 'Gather '\n", " 'Enabled\\n'\n", " '0 '\n", " '- '\n", " 'Scatter '\n", " 'Gather '\n", " 'not '\n", " 'enabled\\n'},\n", " 'SGIntErr': {'access': 'read-only',\n", " 'bit_offset': 8,\n", " 'bit_width': 1,\n", " 'description': 'Scatter '\n", " 'Gather '\n", " 'Internal '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'a '\n", " 'descriptor '\n", " 'with '\n", " 'the '\n", " '\"Complete '\n", " 'bit\" '\n", " 'already '\n", " 'set '\n", " 'is '\n", " 'fetched. '\n", " 'Refer '\n", " 'to '\n", " 'the '\n", " 'Scatter '\n", " 'Gather '\n", " 'Descriptor '\n", " 'section '\n", " 'for '\n", " 'more '\n", " 'information.This '\n", " 'indicates '\n", " 'to '\n", " 'the '\n", " 'SG '\n", " 'Engine '\n", " 'that '\n", " 'the '\n", " 'descriptor '\n", " 'is '\n", " 'a '\n", " 'stale '\n", " 'descriptor. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'SG '\n", " 'Internal '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'SG '\n", " 'Internal '\n", " 'Error '\n", " 'detected. '\n", " 'DMA '\n", " 'Engine '\n", " 'halts. '\n", " 'Note: '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'not '\n", " 'used '\n", " 'and '\n", " 'is '\n", " 'fixed '\n", " 'at '\n", " '0 '\n", " 'when '\n", " 'AXI '\n", " 'DMA '\n", " 'is '\n", " 'configured '\n", " 'for '\n", " 'Direct '\n", " 'Register '\n", " 'Mode.\\n'},\n", " 'SGSlvErr': {'access': 'read-only',\n", " 'bit_offset': 9,\n", " 'bit_width': 1,\n", " 'description': 'Scatter '\n", " 'Gather '\n", " 'Slave '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'slave '\n", " 'read '\n", " 'from '\n", " 'on '\n", " 'the '\n", " 'Memory '\n", " 'Map '\n", " 'interface '\n", " 'issues '\n", " 'a '\n", " 'Slave '\n", " 'error. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'SG '\n", " 'Slave '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'SG '\n", " 'Slave '\n", " 'Error '\n", " 'detected. '\n", " 'DMA '\n", " 'Engine '\n", " 'halts. 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'\n", " 'If '\n", " 'Data '\n", " 'Realignment '\n", " 'Engine '\n", " 'is '\n", " 'not '\n", " 'included, '\n", " 'the '\n", " 'Dstination '\n", " 'Address '\n", " 'must '\n", " 'be '\n", " 'S2MM '\n", " 'Memory '\n", " 'Map '\n", " 'data '\n", " 'width '\n", " 'aligned.\\n'}},\n", " 'size': 32},\n", " 'S2MM_DMACR': {'access': 'read-write',\n", " 'address_offset': 48,\n", " 'description': 'S2MM DMA Control '\n", " 'Register',\n", " 'fields': {'Cyclic_BD_Enable': {'access': 'read-write',\n", " 'bit_offset': 4,\n", " 'bit_width': 1,\n", " 'description': 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'the '\n", " 'DMA '\n", " 'operates '\n", " 'in '\n", " 'Cyclic '\n", " 'Buffer '\n", " 'Descriptor '\n", " '(BD) '\n", " 'mode '\n", " 'without '\n", " 'any '\n", " 'user '\n", " 'intervention. '\n", " 'In '\n", " 'this '\n", " 'mode, '\n", " 'the '\n", " 'Scatter '\n", " 'Gather '\n", " 'module '\n", " 'ignores '\n", " 'the '\n", " 'Completed '\n", " 'bit '\n", " 'of '\n", " 'the '\n", " 'BD. '\n", " 'With '\n", " 'this '\n", " 'bit '\n", " 'set, '\n", " 'you '\n", " 'can '\n", " 'use '\n", " 'the '\n", " 'same '\n", " 'BDs '\n", " 'in '\n", " 'cyclic '\n", " 'manner '\n", " 'without '\n", " 'worrying '\n", " 'about '\n", " 'any '\n", " 'stale '\n", " 'descriptor '\n", " 'errors.\\n'\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'non '\n", " 'functional '\n", " 'when '\n", " 'DMA '\n", " 'operates '\n", " 'in '\n", " 'Multichannel '\n", " 'mode. '\n", " 'or '\n", " 'in '\n", " 'Direct '\n", " 'Register '\n", " 'Mode\\n'},\n", " 'Dly_IrqEn': {'access': 'read-write',\n", " 'bit_offset': 13,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Delay '\n", " 'Timer '\n", " 'Interrupt '\n", " 'Enable. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'allows '\n", " 'error '\n", " 'events '\n", " 'to '\n", " 'generate '\n", " 'an '\n", " 'interrupt '\n", " 'out. '\n", " '0 '\n", " '- '\n", " 'Delay '\n", " 'Interrupt '\n", " 'disabled '\n", " '1 '\n", " '- '\n", " 'Delay '\n", " 'Interrupt '\n", " 'enabled '\n", " 'Note: '\n", " 'Applicable '\n", " 'only '\n", " 'when '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'enabled.\\n'},\n", " 'Err_IrqEn': {'access': 'read-write',\n", " 'bit_offset': 14,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Error '\n", " 'Interrupt '\n", " 'Enable. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'allows '\n", " 'error '\n", " 'events '\n", " 'to '\n", " 'generate '\n", " 'an '\n", " 'interrupt '\n", " 'out. '\n", " '0 '\n", " '- '\n", " 'Error '\n", " 'Interrupt '\n", " 'disabled '\n", " '1 '\n", " '- '\n", " 'Error '\n", " 'Interrupt '\n", " 'enabled\\n'},\n", " 'IOC_IrqEn': {'access': 'read-write',\n", " 'bit_offset': 12,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Complete '\n", " '(IOC) '\n", " 'Interrupt '\n", " 'Enable. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'allows '\n", " 'Interrupt '\n", " 'On '\n", " 'Complete '\n", " 'events '\n", " 'to '\n", " 'generate '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'for '\n", " 'descriptors '\n", " 'with '\n", " 'the '\n", " 'Complete '\n", " 'bit '\n", " 'set. '\n", " '0 '\n", " '- '\n", " 'IOC '\n", " 'Interrupt '\n", " 'disabled '\n", " '1 '\n", " '- '\n", " 'IOC '\n", " 'Interrupt '\n", " 'enabled\\n'},\n", " 'IRQDelay': {'access': 'read-write',\n", " 'bit_offset': 24,\n", " 'bit_width': 8,\n", " 'description': 'Interrupt '\n", " 'Delay '\n", " 'Time '\n", " 'Out. '\n", " 'This '\n", " 'value '\n", " 'is '\n", " 'used '\n", " 'for '\n", " 'setting '\n", " 'the '\n", " 'interrupt '\n", " 'timeout '\n", " 'value. '\n", " 'The '\n", " 'interrupt '\n", " 'timeout '\n", " 'mechanism '\n", " 'causes '\n", " 'the '\n", " 'DMA '\n", " 'engine '\n", " 'to '\n", " 'generate '\n", " 'an '\n", " 'interrupt '\n", " 'after '\n", " 'the '\n", " 'delay '\n", " 'time '\n", " 'period '\n", " 'has '\n", " 'expired. '\n", " 'Timer '\n", " 'begins '\n", " 'counting '\n", " 'at '\n", " 'the '\n", " 'end '\n", " 'of '\n", " 'a '\n", " 'packet '\n", " 'and '\n", " 'resets '\n", " 'with '\n", " 'receipt '\n", " 'of '\n", " 'a '\n", " 'new '\n", " 'packet '\n", " 'or '\n", " 'a '\n", " 'timeout '\n", " 'event '\n", " 'occurs.\\n'\n", " 'Note: '\n", " 'Setting '\n", " 'this '\n", " 'value '\n", " 'to '\n", " 'zero '\n", " 'disables '\n", " 'the '\n", " 'delay '\n", " 'timer '\n", " 'interrupt.\\n'\n", " 'Note: '\n", " 'Applicable '\n", " 'only '\n", " 'when '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'enabled.\\n'},\n", " 'IRQThreshold': {'access': 'read-write',\n", " 'bit_offset': 16,\n", " 'bit_width': 8,\n", " 'description': 'Interrupt '\n", " 'Threshold. '\n", " 'This '\n", " 'value '\n", " 'is '\n", " 'used '\n", " 'for '\n", " 'setting '\n", " 'the '\n", " 'interrupt '\n", " 'threshold. '\n", " 'When '\n", " 'IOC '\n", " 'interrupt '\n", " 'events '\n", " 'occur, '\n", " 'an '\n", " 'internal '\n", " 'counter '\n", " 'counts '\n", " 'down '\n", " 'from '\n", " 'the '\n", " 'Interrupt '\n", " 'Threshold '\n", " 'setting. '\n", " 'When '\n", " 'the '\n", " 'count '\n", " 'reaches '\n", " 'zero, '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'is '\n", " 'generated '\n", " 'by '\n", " 'the '\n", " 'DMA '\n", " 'engine.\\n'\n", " 'Note: '\n", " 'The '\n", " 'minimum '\n", " 'setting '\n", " 'for '\n", " 'the '\n", " 'threshold '\n", " 'is '\n", " '0x01. '\n", " 'A '\n", " 'write '\n", " 'of '\n", " '0x00 '\n", " 'to '\n", " 'this '\n", " 'register '\n", " 'has '\n", " 'no '\n", " 'effect.\\n'\n", " 'Note: '\n", " 'Applicable '\n", " 'only '\n", " 'when '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'enabled.\\n'},\n", " 'Keyhole': {'access': 'read-write',\n", " 'bit_offset': 3,\n", " 'bit_width': 1,\n", " 'description': 'Keyhole '\n", " 'Write. '\n", " 'Setting '\n", " 'this '\n", " 'bit '\n", " 'to '\n", " '1 '\n", " 'causes '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'initiate '\n", " 'S2MM '\n", " 'writes '\n", " '(AXI4 '\n", " 'Writes) '\n", " 'in '\n", " 'non-incrementing '\n", " 'address '\n", " 'mode '\n", " '(Fixed '\n", " 'Address '\n", " 'Burst '\n", " 'transfer '\n", " 'on '\n", " 'AXI4). '\n", " 'This '\n", " 'bit '\n", " 'can '\n", " 'be '\n", " 'modified '\n", " 'when '\n", " 'AXI '\n", " 'DMA '\n", " 'is '\n", " 'in '\n", " 'idle. '\n", " 'When '\n", " 'enabling '\n", " 'Key '\n", " 'hole '\n", " 'operation '\n", " 'the '\n", " 'maximum '\n", " 'burst '\n", " 'length '\n", " 'cannot '\n", " 'be '\n", " 'more '\n", " 'than '\n", " '16. '\n", " 'This '\n", " 'bit '\n", " 'should '\n", " 'not '\n", " 'be '\n", " 'set '\n", " 'when '\n", " 'DRE '\n", " 'is '\n", " 'enabled.\\n'\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'non '\n", " 'functional '\n", " 'when '\n", " 'DMA '\n", " 'is '\n", " 'used '\n", " 'in '\n", " 'multichannel '\n", " 'mode.\\n'},\n", " 'RS': {'access': 'read-write',\n", " 'bit_offset': 0,\n", " 'bit_width': 1,\n", " 'description': 'Run '\n", " '/ '\n", " 'Stop '\n", " 'control '\n", " 'for '\n", " 'controlling '\n", " 'running '\n", " 'and '\n", " 'stopping '\n", " 'of '\n", " 'the '\n", " 'DMA '\n", " 'channel.\\n'\n", " ' '\n", " '0 '\n", " '- '\n", " 'Stop, '\n", " 'DMA '\n", " 'stops '\n", " 'when '\n", " 'current '\n", " '(if '\n", " 'any) '\n", " 'DMA '\n", " 'operations '\n", " 'are '\n", " 'complete. '\n", " 'For '\n", " 'Scatter '\n", " '/ '\n", " 'Gather '\n", " 'Mode '\n", " 'pending '\n", " 'commands/transfers '\n", " 'are '\n", " 'flushed '\n", " 'or '\n", " 'completed. \\n'\n", " ' '\n", " 'AXI4-Stream '\n", " 'outs '\n", " 'are '\n", " 'potentially '\n", " 'terminated '\n", " 'early. '\n", " 'Descriptors '\n", " 'in '\n", " 'the '\n", " 'update '\n", " 'queue '\n", " 'are '\n", " 'allowed '\n", " 'to '\n", " 'finish '\n", " 'updating '\n", " 'to '\n", " 'remote '\n", " 'memory '\n", " 'before '\n", " 'engine '\n", " 'halt.\\n'\n", " ' '\n", " 'For '\n", " 'Direct '\n", " 'Register '\n", " 'mode '\n", " 'pending '\n", " 'commands/transfers '\n", " 'are '\n", " 'flushed '\n", " 'or '\n", " 'completed. '\n", " 'AXI4-Stream '\n", " 'outs '\n", " 'are '\n", " 'potentially '\n", " 'terminated. '\n", " 'Data '\n", " 'integrity '\n", " 'on '\n", " 'S2MM '\n", " 'AXI4 '\n", " 'cannot '\n", " 'be '\n", " 'guaranteed.\\n'\n", " ' '\n", " 'The '\n", " 'halted '\n", " 'bit '\n", " 'in '\n", " 'the '\n", " 'DMA '\n", " 'Status '\n", " 'register '\n", " 'asserts '\n", " 'to '\n", " '1 '\n", " 'when '\n", " 'the '\n", " 'DMA '\n", " 'engine '\n", " 'is '\n", " 'halted. '\n", " 'This '\n", " 'bit '\n", " 'is '\n", " 'cleared '\n", " 'by '\n", " 'AXI '\n", " 'DMA '\n", " 'hardware '\n", " 'when '\n", " 'an '\n", " 'error '\n", " 'occurs. '\n", " 'The '\n", " 'CPU '\n", " 'can '\n", " 'also '\n", " 'choose '\n", " 'to '\n", " 'clear '\n", " 'this '\n", " 'bit '\n", " 'to '\n", " 'stop '\n", " 'DMA '\n", " 'operations.\\n'\n", " ' '\n", " '1 '\n", " '- '\n", " 'Run, '\n", " 'Start '\n", " 'DMA '\n", " 'operations. '\n", " 'The '\n", " 'halted '\n", " 'bit '\n", " 'in '\n", " 'the '\n", " 'DMA '\n", " 'Status '\n", " 'register '\n", " 'deasserts '\n", " 'to '\n", " '0 '\n", " 'when '\n", " 'the '\n", " 'DMA '\n", " 'engine '\n", " 'begins '\n", " 'operations.\\n'},\n", " 'Reset': {'access': 'read-write',\n", " 'bit_offset': 2,\n", " 'bit_width': 1,\n", " 'description': 'Soft '\n", " 'reset '\n", " 'for '\n", " 'resetting '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'core. '\n", " 'Setting '\n", " 'this '\n", " 'bit '\n", " 'to '\n", " 'a '\n", " '1 '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'be '\n", " 'reset. '\n", " 'Reset '\n", " 'is '\n", " 'accomplished '\n", " 'gracefully. '\n", " 'Pending '\n", " 'commands/transfers '\n", " 'are '\n", " 'flushed '\n", " 'or '\n", " 'completed.\\n'\n", " 'AXI4-Stream '\n", " 'outs '\n", " 'are '\n", " 'terminated '\n", " 'early, '\n", " 'if '\n", " 'necessary '\n", " 'with '\n", " 'associated '\n", " 'TLAST. '\n", " 'Setting '\n", " 'either '\n", " 'MM2S_DMACR.Reset '\n", " '= '\n", " '1 '\n", " 'or '\n", " 'S2MM_DMACR.Reset '\n", " '= '\n", " '1 '\n", " 'resets '\n", " 'the '\n", " 'entire '\n", " 'AXI '\n", " 'DMA '\n", " 'engine. '\n", " 'After '\n", " 'completion '\n", " 'of '\n", " 'a '\n", " 'soft '\n", " 'reset, '\n", " 'all '\n", " 'registers '\n", " 'and '\n", " 'bits '\n", " 'are '\n", " 'in '\n", " 'the '\n", " 'Reset '\n", " 'State. '\n", " '0 '\n", " '- '\n", " 'Reset '\n", " 'not '\n", " 'in '\n", " 'progress. '\n", " 'Normal '\n", " 'operation. '\n", " '1 '\n", " '- '\n", " 'Reset '\n", " 'in '\n", " 'progress\\n'}},\n", " 'size': 32},\n", " 'S2MM_DMASR': {'access': 'read-write',\n", " 'address_offset': 52,\n", " 'description': 'S2MM DMA Status '\n", " 'Register',\n", " 'fields': {'DMADecErr': {'access': 'read-only',\n", " 'bit_offset': 6,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Decode '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'address '\n", " 'request '\n", " 'points '\n", " 'to '\n", " 'an '\n", " 'invalid '\n", " 'address. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'DMA '\n", " 'Decode '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'Decode '\n", " 'Error '\n", " 'detected.\\n'},\n", " 'DMAIntErr': {'access': 'read-only',\n", " 'bit_offset': 4,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Internal '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'buffer '\n", " 'length '\n", " 'specified '\n", " 'in '\n", " 'the '\n", " 'fetched '\n", " 'descriptor '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0. '\n", " 'Also, '\n", " 'when '\n", " 'in '\n", " 'Scatter '\n", " 'Gather '\n", " 'Mode '\n", " 'and '\n", " 'using '\n", " 'the '\n", " 'status '\n", " 'app '\n", " 'length '\n", " 'field, '\n", " 'this '\n", " 'error '\n", " 'occurs '\n", " 'when '\n", " 'the '\n", " 'Status '\n", " 'AXI4-Stream '\n", " 'packet '\n", " 'RxLength '\n", " 'field '\n", " 'does '\n", " 'not '\n", " 'match '\n", " 'the '\n", " 'S2MM '\n", " 'packet '\n", " 'being '\n", " 'received '\n", " 'by '\n", " 'the '\n", " 'S_AXIS_S2MM '\n", " 'interface. '\n", " 'When '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'disabled, '\n", " 'this '\n", " 'error '\n", " 'is '\n", " 'flagged '\n", " 'if '\n", " 'any '\n", " 'error '\n", " 'occurs '\n", " 'during '\n", " 'Memory '\n", " 'write '\n", " 'or '\n", " 'if '\n", " 'the '\n", " 'incoming '\n", " 'packet '\n", " 'is '\n", " 'bigger '\n", " 'than '\n", " 'what '\n", " 'is '\n", " 'specified '\n", " 'in '\n", " 'the '\n", " 'DMA '\n", " 'length '\n", " 'register.\\n'\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'DMA '\n", " 'Internal '\n", " 'Errors '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'Internal '\n", " 'Error '\n", " 'detected.\\n'},\n", " 'DMASlvErr': {'access': 'read-only',\n", " 'bit_offset': 5,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Slave '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'occurs '\n", " 'if '\n", " 'the '\n", " 'slave '\n", " 'read '\n", " 'from '\n", " 'the '\n", " 'Memory '\n", " 'Map '\n", " 'interface '\n", " 'issues '\n", " 'a '\n", " 'Slave '\n", " 'Error. '\n", " 'This '\n", " 'error '\n", " 'condition '\n", " 'causes '\n", " 'the '\n", " 'AXI '\n", " 'DMA '\n", " 'to '\n", " 'halt '\n", " 'gracefully. '\n", " 'The '\n", " 'DMACR.RS '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '0, '\n", " 'and '\n", " 'when '\n", " 'the '\n", " 'engine '\n", " 'has '\n", " 'completely '\n", " 'shut '\n", " 'down, '\n", " 'the '\n", " 'DMASR.Halted '\n", " 'bit '\n", " 'is '\n", " 'set '\n", " 'to '\n", " '1. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'DMA '\n", " 'Slave '\n", " 'Errors. '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'Slave '\n", " 'Error '\n", " 'detected.\\n'},\n", " 'Dly_Irq': {'access': 'read-write',\n", " 'bit_offset': 13,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Delay. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'indicates '\n", " 'an '\n", " 'interrupt '\n", " 'event '\n", " 'was '\n", " 'generated '\n", " 'on '\n", " 'delay '\n", " 'timer '\n", " 'time '\n", " 'out. '\n", " 'If '\n", " 'the '\n", " 'corresponding '\n", " 'bit '\n", " 'is '\n", " 'enabled '\n", " 'in '\n", " 'the '\n", " 'S2MM_DMACR '\n", " '(Dly_IrqEn '\n", " '= '\n", " '1), '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'is '\n", " 'generated '\n", " 'from '\n", " 'the '\n", " 'AXI '\n", " 'DMA. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'Delay '\n", " 'Interrupt. '\n", " '1 '\n", " '- '\n", " 'Delay '\n", " 'Interrupt '\n", " 'detected.1 '\n", " '= '\n", " 'IOC '\n", " 'Interrupt '\n", " 'detected. '\n", " 'Writing '\n", " 'a '\n", " '1 '\n", " 'to '\n", " 'this '\n", " 'bit '\n", " 'will '\n", " 'clear '\n", " 'it. '\n", " 'Note: '\n", " 'Applicable '\n", " 'only '\n", " 'when '\n", " 'Scatter '\n", " 'Gather '\n", " 'is '\n", " 'enabled. \\n'},\n", " 'Err_Irq': {'access': 'read-write',\n", " 'bit_offset': 14,\n", " 'bit_width': 1,\n", " 'description': 'Interrupt '\n", " 'on '\n", " 'Error. '\n", " 'When '\n", " 'set '\n", " 'to '\n", " '1, '\n", " 'indicates '\n", " 'an '\n", " 'interrupt '\n", " 'event '\n", " 'was '\n", " 'generated '\n", " 'on '\n", " 'error. '\n", " 'If '\n", " 'the '\n", " 'corresponding '\n", " 'bit '\n", " 'is '\n", " 'enabled '\n", " 'in '\n", " 'the '\n", " 'S2MM_DMACR '\n", " '(Err_IrqEn '\n", " '= '\n", " '1), '\n", " 'an '\n", " 'interrupt '\n", " 'out '\n", " 'is '\n", " 'generated '\n", " 'from '\n", " 'the '\n", " 'AXI '\n", " 'DMA.\\n'\n", " 'Writing '\n", " 'a '\n", " '1 '\n", " 'to '\n", " 'this '\n", " 'bit '\n", " 'will '\n", " 'clear '\n", " 'it. '\n", " '0 '\n", " '- '\n", " 'No '\n", " 'error '\n", " 'Interrupt. '\n", " '1 '\n", " '- '\n", " 'Error '\n", " 'interrupt '\n", " 'detected.\\n'},\n", " 'Halted': {'access': 'read-only',\n", " 'bit_offset': 0,\n", " 'bit_width': 1,\n", " 'description': 'DMA '\n", " 'Channel '\n", " 'Halted. '\n", " 'Indicates '\n", " 'the '\n", " 'run/stop '\n", " 'state '\n", " 'of '\n", " 'the '\n", " 'DMA '\n", " 'channel. '\n", " '0 '\n", " '- '\n", " 'DMA '\n", " 'channel '\n", " 'running. '\n", " '1 '\n", " '- '\n", " 'DMA '\n", " 'channel '\n", " 'halted. '\n", " 'For '\n", " 'Scatter/Gather '\n", " 'Mode '\n", " 'this '\n", " 'bit '\n", " 'gets '\n", " 'set '\n", " 'when '\n", " 'DMACR.RS '\n", " '= '\n", " '0 '\n", " 'and '\n", " 'DMA '\n", " 'and '\n", " 'SG '\n", " 'operations '\n", " 'have '\n", " 'halted. '\n", " 'For '\n", " 'Direct '\n", " 'Register '\n", " 'Mode '\n", " 'this '\n", " 'bit '\n", " 'gets '\n", " 'set '\n", " 'when '\n", " 'DMACR.RS '\n", " '= '\n", " '0 '\n", " 'and '\n", " 'DMA '\n", " 'operations '\n", " 'have '\n", " 'halted. '\n", " 'There '\n", " 'can '\n", " 'be '\n", " 'a '\n", " 'lag '\n", " 'of '\n", " 'time '\n", " 'between '\n", " 'when '\n", " 'DMACR.RS '\n", " '= '\n", " '0 '\n", " 'and '\n", " 'when '\n", " 'DMASR.Halted '\n", " '= '\n", " '1 \\n'\n", " 'Note: '\n", " 'When '\n", " 'halted '\n", " '(RS= '\n", " '0 '\n", " 'and '\n", " 'Halted '\n", " '= '\n", " '1), '\n", " 'writing '\n", " 'to '\n", " 'CURDESC_PTR '\n", " 'or '\n", " 'TAILDESC_PTR '\n", " 'pointer '\n", " 'registers '\n", " 'has '\n", " 'no '\n", " 'effect '\n", " 'on '\n", " 'DMA '\n", " 'operations '\n", " 'when '\n", " 'in '\n", " 'Scatter '\n", " 'Gather '\n", " 'Mode. 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'false',\n", " 'C_ADC_Bypass_BG_Cal32': 'false',\n", " 'C_ADC_Bypass_BG_Cal33': 'false',\n", " 'C_ADC_CalOpt_Mode00': '1',\n", " 'C_ADC_CalOpt_Mode01': '1',\n", " 'C_ADC_CalOpt_Mode02': '1',\n", " 'C_ADC_CalOpt_Mode03': '1',\n", " 'C_ADC_CalOpt_Mode10': '1',\n", " 'C_ADC_CalOpt_Mode11': '1',\n", " 'C_ADC_CalOpt_Mode12': '1',\n", " 'C_ADC_CalOpt_Mode13': '1',\n", " 'C_ADC_CalOpt_Mode20': '2',\n", " 'C_ADC_CalOpt_Mode21': '2',\n", " 'C_ADC_CalOpt_Mode22': '1',\n", " 'C_ADC_CalOpt_Mode23': '1',\n", " 'C_ADC_CalOpt_Mode30': '1',\n", " 'C_ADC_CalOpt_Mode31': '1',\n", " 'C_ADC_CalOpt_Mode32': '1',\n", " 'C_ADC_CalOpt_Mode33': '1',\n", " 'C_ADC_Coarse_Mixer_Freq00': '3',\n", " 'C_ADC_Coarse_Mixer_Freq01': '3',\n", " 'C_ADC_Coarse_Mixer_Freq02': '0',\n", " 'C_ADC_Coarse_Mixer_Freq03': '0',\n", " 'C_ADC_Coarse_Mixer_Freq10': '0',\n", " 'C_ADC_Coarse_Mixer_Freq11': '0',\n", " 'C_ADC_Coarse_Mixer_Freq12': '0',\n", " 'C_ADC_Coarse_Mixer_Freq13': '0',\n", " 'C_ADC_Coarse_Mixer_Freq20': '0',\n", " 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'C_ADC_Data_Width11': '8',\n", " 'C_ADC_Data_Width12': '8',\n", " 'C_ADC_Data_Width13': '8',\n", " 'C_ADC_Data_Width20': '1',\n", " 'C_ADC_Data_Width21': '1',\n", " 'C_ADC_Data_Width22': '8',\n", " 'C_ADC_Data_Width23': '8',\n", " 'C_ADC_Data_Width30': '8',\n", " 'C_ADC_Data_Width31': '8',\n", " 'C_ADC_Data_Width32': '8',\n", " 'C_ADC_Data_Width33': '8',\n", " 'C_ADC_Debug': 'false',\n", " 'C_ADC_Decimation_Mode00': '0',\n", " 'C_ADC_Decimation_Mode01': '0',\n", " 'C_ADC_Decimation_Mode02': '0',\n", " 'C_ADC_Decimation_Mode03': '0',\n", " 'C_ADC_Decimation_Mode10': '0',\n", " 'C_ADC_Decimation_Mode11': '0',\n", " 'C_ADC_Decimation_Mode12': '0',\n", " 'C_ADC_Decimation_Mode13': '0',\n", " 'C_ADC_Decimation_Mode20': '16',\n", " 'C_ADC_Decimation_Mode21': '16',\n", " 'C_ADC_Decimation_Mode22': '0',\n", " 'C_ADC_Decimation_Mode23': '0',\n", " 'C_ADC_Decimation_Mode30': '0',\n", " 'C_ADC_Decimation_Mode31': '0',\n", " 'C_ADC_Decimation_Mode32': '0',\n", " 'C_ADC_Decimation_Mode33': '0',\n", " 'C_ADC_Dither00': 'true',\n", " 'C_ADC_Dither01': 'true',\n", " 'C_ADC_Dither02': 'true',\n", " 'C_ADC_Dither03': 'true',\n", " 'C_ADC_Dither10': 'true',\n", " 'C_ADC_Dither11': 'true',\n", " 'C_ADC_Dither12': 'true',\n", " 'C_ADC_Dither13': 'true',\n", " 'C_ADC_Dither20': 'true',\n", " 'C_ADC_Dither21': 'true',\n", " 'C_ADC_Dither22': 'true',\n", " 'C_ADC_Dither23': 'true',\n", " 'C_ADC_Dither30': 'true',\n", " 'C_ADC_Dither31': 'true',\n", " 'C_ADC_Dither32': 'true',\n", " 'C_ADC_Dither33': 'true',\n", " 'C_ADC_MTS_Variable_Fabric_Width': 'false',\n", " 'C_ADC_Mixer_Mode00': '2',\n", " 'C_ADC_Mixer_Mode01': '2',\n", " 'C_ADC_Mixer_Mode02': '2',\n", " 'C_ADC_Mixer_Mode03': '2',\n", " 'C_ADC_Mixer_Mode10': '2',\n", " 'C_ADC_Mixer_Mode11': '2',\n", " 'C_ADC_Mixer_Mode12': '2',\n", " 'C_ADC_Mixer_Mode13': '2',\n", " 'C_ADC_Mixer_Mode20': '0',\n", " 'C_ADC_Mixer_Mode21': '0',\n", " 'C_ADC_Mixer_Mode22': '2',\n", " 'C_ADC_Mixer_Mode23': '2',\n", " 'C_ADC_Mixer_Mode30': '2',\n", " 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'C_ADC_Neg_Quadrature13': 'false',\n", " 'C_ADC_Neg_Quadrature20': 'false',\n", " 'C_ADC_Neg_Quadrature21': 'false',\n", " 'C_ADC_Neg_Quadrature22': 'false',\n", " 'C_ADC_Neg_Quadrature23': 'false',\n", " 'C_ADC_Neg_Quadrature30': 'false',\n", " 'C_ADC_Neg_Quadrature31': 'false',\n", " 'C_ADC_Neg_Quadrature32': 'false',\n", " 'C_ADC_Neg_Quadrature33': 'false',\n", " 'C_ADC_Nyquist00': '0',\n", " 'C_ADC_Nyquist01': '0',\n", " 'C_ADC_Nyquist02': '0',\n", " 'C_ADC_Nyquist03': '0',\n", " 'C_ADC_Nyquist10': '0',\n", " 'C_ADC_Nyquist11': '0',\n", " 'C_ADC_Nyquist12': '0',\n", " 'C_ADC_Nyquist13': '0',\n", " 'C_ADC_Nyquist20': '0',\n", " 'C_ADC_Nyquist21': '0',\n", " 'C_ADC_Nyquist22': '0',\n", " 'C_ADC_Nyquist23': '0',\n", " 'C_ADC_Nyquist30': '0',\n", " 'C_ADC_Nyquist31': '0',\n", " 'C_ADC_Nyquist32': '0',\n", " 'C_ADC_Nyquist33': '0',\n", " 'C_ADC_OBS00': 'false',\n", " 'C_ADC_OBS01': 'false',\n", " 'C_ADC_OBS02': 'false',\n", " 'C_ADC_OBS03': 'false',\n", " 'C_ADC_OBS10': 'false',\n", " 'C_ADC_OBS11': 'false',\n", " 'C_ADC_OBS12': 'false',\n", " 'C_ADC_OBS13': 'false',\n", " 'C_ADC_OBS20': 'false',\n", " 'C_ADC_OBS21': 'false',\n", " 'C_ADC_OBS22': 'false',\n", " 'C_ADC_OBS23': 'false',\n", " 'C_ADC_OBS30': 'false',\n", " 'C_ADC_OBS31': 'false',\n", " 'C_ADC_OBS32': 'false',\n", " 'C_ADC_OBS33': 'false',\n", " 'C_ADC_OBS_Data_Width00': '8',\n", " 'C_ADC_OBS_Data_Width01': '8',\n", " 'C_ADC_OBS_Data_Width02': '8',\n", " 'C_ADC_OBS_Data_Width03': '8',\n", " 'C_ADC_OBS_Data_Width10': '8',\n", " 'C_ADC_OBS_Data_Width11': '8',\n", " 'C_ADC_OBS_Data_Width12': '8',\n", " 'C_ADC_OBS_Data_Width13': '8',\n", " 'C_ADC_OBS_Data_Width20': '1',\n", " 'C_ADC_OBS_Data_Width21': '1',\n", " 'C_ADC_OBS_Data_Width22': '8',\n", " 'C_ADC_OBS_Data_Width23': '8',\n", " 'C_ADC_OBS_Data_Width30': '8',\n", " 'C_ADC_OBS_Data_Width31': '8',\n", " 'C_ADC_OBS_Data_Width32': '8',\n", " 'C_ADC_OBS_Data_Width33': '8',\n", " 'C_ADC_OBS_Decimation_Mode00': '0',\n", " 'C_ADC_OBS_Decimation_Mode01': '0',\n", " 'C_ADC_OBS_Decimation_Mode02': '0',\n", " 'C_ADC_OBS_Decimation_Mode03': '0',\n", " 'C_ADC_OBS_Decimation_Mode10': '0',\n", " 'C_ADC_OBS_Decimation_Mode11': '0',\n", " 'C_ADC_OBS_Decimation_Mode12': '0',\n", " 'C_ADC_OBS_Decimation_Mode13': '0',\n", " 'C_ADC_OBS_Decimation_Mode20': '16',\n", " 'C_ADC_OBS_Decimation_Mode21': '16',\n", " 'C_ADC_OBS_Decimation_Mode22': '0',\n", " 'C_ADC_OBS_Decimation_Mode23': '0',\n", " 'C_ADC_OBS_Decimation_Mode30': '0',\n", " 'C_ADC_OBS_Decimation_Mode31': '0',\n", " 'C_ADC_OBS_Decimation_Mode32': '0',\n", " 'C_ADC_OBS_Decimation_Mode33': '0',\n", " 'C_ADC_RESERVED_1_00': 'false',\n", " 'C_ADC_RESERVED_1_01': 'false',\n", " 'C_ADC_RESERVED_1_02': 'false',\n", " 'C_ADC_RESERVED_1_03': 'false',\n", " 'C_ADC_RESERVED_1_10': 'false',\n", " 'C_ADC_RESERVED_1_11': 'false',\n", " 'C_ADC_RESERVED_1_12': 'false',\n", " 'C_ADC_RESERVED_1_13': 'false',\n", " 'C_ADC_RESERVED_1_20': 'false',\n", " 'C_ADC_RESERVED_1_21': 'false',\n", " 'C_ADC_RESERVED_1_22': 'false',\n", " 'C_ADC_RESERVED_1_23': 'false',\n", " 'C_ADC_RESERVED_1_30': 'false',\n", " 'C_ADC_RESERVED_1_31': 'false',\n", " 'C_ADC_RESERVED_1_32': 'false',\n", " 'C_ADC_RESERVED_1_33': 'false',\n", " 'C_ADC_RTS': 'false',\n", " 'C_ADC_Slice00_Enable': 'false',\n", " 'C_ADC_Slice01_Enable': 'false',\n", " 'C_ADC_Slice02_Enable': 'false',\n", " 'C_ADC_Slice03_Enable': 'false',\n", " 'C_ADC_Slice10_Enable': 'false',\n", " 'C_ADC_Slice11_Enable': 'false',\n", " 'C_ADC_Slice12_Enable': 'false',\n", " 'C_ADC_Slice13_Enable': 'false',\n", " 'C_ADC_Slice20_Enable': 'true',\n", " 'C_ADC_Slice21_Enable': 'true',\n", " 'C_ADC_Slice22_Enable': 'false',\n", " 'C_ADC_Slice23_Enable': 'false',\n", " 'C_ADC_Slice30_Enable': 'false',\n", " 'C_ADC_Slice31_Enable': 'false',\n", " 'C_ADC_Slice32_Enable': 'false',\n", " 'C_ADC_Slice33_Enable': 'false',\n", " 'C_ADC_TDD_RTS00': '0',\n", " 'C_ADC_TDD_RTS01': '0',\n", " 'C_ADC_TDD_RTS02': '0',\n", " 'C_ADC_TDD_RTS03': '0',\n", " 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'false',\n", " 'DAC_Invsinc_Ctrl02': 'false',\n", " 'DAC_Invsinc_Ctrl03': 'false',\n", " 'DAC_Invsinc_Ctrl10': 'false',\n", " 'DAC_Invsinc_Ctrl11': 'false',\n", " 'DAC_Invsinc_Ctrl12': 'false',\n", " 'DAC_Invsinc_Ctrl13': 'false',\n", " 'DAC_Invsinc_Ctrl20': 'false',\n", " 'DAC_Invsinc_Ctrl21': 'false',\n", " 'DAC_Invsinc_Ctrl22': 'false',\n", " 'DAC_Invsinc_Ctrl23': 'false',\n", " 'DAC_Invsinc_Ctrl30': 'false',\n", " 'DAC_Invsinc_Ctrl31': 'false',\n", " 'DAC_Invsinc_Ctrl32': 'false',\n", " 'DAC_Invsinc_Ctrl33': 'false',\n", " 'DAC_MTS_Variable_Fabric_Width': 'false',\n", " 'DAC_Mixer_Mode00': '0',\n", " 'DAC_Mixer_Mode01': '0',\n", " 'DAC_Mixer_Mode02': '2',\n", " 'DAC_Mixer_Mode03': '0',\n", " 'DAC_Mixer_Mode10': '0',\n", " 'DAC_Mixer_Mode11': '0',\n", " 'DAC_Mixer_Mode12': '2',\n", " 'DAC_Mixer_Mode13': '0',\n", " 'DAC_Mixer_Mode20': '0',\n", " 'DAC_Mixer_Mode21': '0',\n", " 'DAC_Mixer_Mode22': '2',\n", " 'DAC_Mixer_Mode23': '2',\n", " 'DAC_Mixer_Mode30': '0',\n", " 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'VNC_Include_Fs2_Change': 'true',\n", " 'VNC_Include_OIS_Change': 'true',\n", " 'VNC_Testing': 'false',\n", " 'WUSER_BITS_PER_BYTE': '0',\n", " 'WUSER_WIDTH': '0',\n", " 'disable_bg_cal_en': '1',\n", " 'mADC_Band': '0',\n", " 'mADC_Bypass_BG_Cal00': 'false',\n", " 'mADC_Bypass_BG_Cal01': 'false',\n", " 'mADC_Bypass_BG_Cal02': 'false',\n", " 'mADC_Bypass_BG_Cal03': 'false',\n", " 'mADC_CalOpt_Mode00': '2',\n", " 'mADC_CalOpt_Mode01': '2',\n", " 'mADC_CalOpt_Mode02': '1',\n", " 'mADC_CalOpt_Mode03': '1',\n", " 'mADC_Coarse_Mixer_Freq00': '0',\n", " 'mADC_Coarse_Mixer_Freq01': '0',\n", " 'mADC_Coarse_Mixer_Freq02': '0',\n", " 'mADC_Coarse_Mixer_Freq03': '0',\n", " 'mADC_Data_Type00': '1',\n", " 'mADC_Data_Type01': '1',\n", " 'mADC_Data_Type02': '0',\n", " 'mADC_Data_Type03': '0',\n", " 'mADC_Data_Width00': '1',\n", " 'mADC_Data_Width01': '1',\n", " 'mADC_Data_Width02': '8',\n", " 'mADC_Data_Width03': '8',\n", " 'mADC_Decimation_Mode00': '16',\n", " 'mADC_Decimation_Mode01': '16',\n", " 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'mDAC_Mixer_Type02': '3',\n", " 'mDAC_Mixer_Type03': '3',\n", " 'mDAC_Mode00': '0',\n", " 'mDAC_Mode01': '0',\n", " 'mDAC_Mode02': '0',\n", " 'mDAC_Mode03': '0',\n", " 'mDAC_Multi_Tile_Sync': 'false',\n", " 'mDAC_NCO_Freq00': '0.0',\n", " 'mDAC_NCO_Freq01': '0.0',\n", " 'mDAC_NCO_Freq02': '0.0',\n", " 'mDAC_NCO_Freq03': '0.0',\n", " 'mDAC_NCO_Phase00': '0',\n", " 'mDAC_NCO_Phase01': '0',\n", " 'mDAC_NCO_Phase02': '0',\n", " 'mDAC_NCO_Phase03': '0',\n", " 'mDAC_Neg_Quadrature00': 'false',\n", " 'mDAC_Neg_Quadrature01': 'false',\n", " 'mDAC_Neg_Quadrature02': 'false',\n", " 'mDAC_Neg_Quadrature03': 'false',\n", " 'mDAC_Nyquist00': '0',\n", " 'mDAC_Nyquist01': '0',\n", " 'mDAC_Nyquist02': '0',\n", " 'mDAC_Nyquist03': '0',\n", " 'mDAC_Outclk_Freq': '50.000',\n", " 'mDAC_PLL_Enable': 'false',\n", " 'mDAC_RESERVED_1_00': 'false',\n", " 'mDAC_RESERVED_1_01': 'false',\n", " 'mDAC_RESERVED_1_02': 'false',\n", " 'mDAC_RESERVED_1_03': 'false',\n", " 'mDAC_Refclk_Div': '1',\n", " 'mDAC_Refclk_Freq': '6400.000',\n", " 'mDAC_Sampling_Rate': '6.4',\n", " 'mDAC_Slice00_Enable': 'false',\n", " 'mDAC_Slice01_Enable': 'false',\n", " 'mDAC_Slice02_Enable': 'false',\n", " 'mDAC_Slice03_Enable': 'false',\n", " 'mDAC_TDD_RTS00': '0',\n", " 'mDAC_TDD_RTS01': '0',\n", " 'mDAC_TDD_RTS02': '0',\n", " 'mDAC_TDD_RTS03': '0',\n", " 'mDAC_VOP': '20.0',\n", " 'production_simulation': '0',\n", " 'tb_adc_fft': 'true',\n", " 'tb_dac_fft': 'true',\n", " 'use_bram': '1'},\n", " 'phys_addr': 2684616704,\n", " 'registers': {},\n", " 'state': None,\n", " 'type': 'xilinx.com:ip:usp_rf_data_converter:2.6'},\n", " 'zynq_ultra_ps_e_0': {'device': ,\n", " 'driver': ,\n", " 'gpio': {},\n", " 'interrupts': {},\n", " 'parameters': {'ADDR_WIDTH': '40',\n", " 'ARUSER_WIDTH': '16',\n", " 'AWUSER_WIDTH': '16',\n", " 'BUSER_WIDTH': '0',\n", " 'CAN0_BOARD_INTERFACE': 'custom',\n", " 'CAN1_BOARD_INTERFACE': 'custom',\n", " 'CLK_DOMAIN': 'design_1_zynq_ultra_ps_e_0_0_pl_clk0',\n", " 'CSU_BOARD_INTERFACE': 'custom',\n", " 'C_BASEADDR': '0x00000000',\n", " 'C_DP_USE_AUDIO': '0',\n", " 'C_DP_USE_VIDEO': '0',\n", " 'C_EMIO_GPIO_WIDTH': '1',\n", " 'C_EN_EMIO_TRACE': '0',\n", " 'C_EN_FIFO_ENET0': '0',\n", " 'C_EN_FIFO_ENET1': '0',\n", " 'C_EN_FIFO_ENET2': '0',\n", " 'C_EN_FIFO_ENET3': '0',\n", " 'C_HIGHADDR': '0x7FFFFFFF',\n", " 'C_MAXIGP0_DATA_WIDTH': '128',\n", " 'C_MAXIGP1_DATA_WIDTH': '128',\n", " 'C_MAXIGP2_DATA_WIDTH': '32',\n", " 'C_NUM_F2P_0_INTR_INPUTS': '1',\n", " 'C_NUM_F2P_1_INTR_INPUTS': '1',\n", " 'C_NUM_FABRIC_RESETS': '1',\n", " 'C_PL_CLK0_BUF': 'TRUE',\n", " 'C_PL_CLK1_BUF': 'FALSE',\n", " 'C_PL_CLK2_BUF': 'FALSE',\n", " 'C_PL_CLK3_BUF': 'FALSE',\n", " 'C_SAXIGP0_DATA_WIDTH': '128',\n", " 'C_SAXIGP1_DATA_WIDTH': '128',\n", " 'C_SAXIGP2_DATA_WIDTH': '128',\n", " 'C_SAXIGP3_DATA_WIDTH': '128',\n", " 'C_SAXIGP4_DATA_WIDTH': '128',\n", " 'C_SAXIGP5_DATA_WIDTH': '128',\n", " 'C_SAXIGP6_DATA_WIDTH': '128',\n", " 'C_SD0_INTERNAL_BUS_WIDTH': '4',\n", " 'C_SD1_INTERNAL_BUS_WIDTH': '5',\n", " 'C_TRACE_DATA_WIDTH': '32',\n", " 'C_TRACE_PIPELINE_WIDTH': '8',\n", " 'C_USE_DEBUG_TEST': '0',\n", " 'C_USE_DIFF_RW_CLK_GP0': '0',\n", " 'C_USE_DIFF_RW_CLK_GP1': '0',\n", " 'C_USE_DIFF_RW_CLK_GP2': '0',\n", " 'C_USE_DIFF_RW_CLK_GP3': '0',\n", " 'C_USE_DIFF_RW_CLK_GP4': '0',\n", " 'C_USE_DIFF_RW_CLK_GP5': '0',\n", " 'C_USE_DIFF_RW_CLK_GP6': '0',\n", " 'Component_Name': 'design_1_zynq_ultra_ps_e_0_0',\n", " 'DATA_WIDTH': '128',\n", " 'DP_BOARD_INTERFACE': 'custom',\n", " 'EDK_IPTYPE': 'PERIPHERAL',\n", " 'FREQ_HZ': '149999969',\n", " 'GEM0_BOARD_INTERFACE': 'custom',\n", " 'GEM1_BOARD_INTERFACE': 'custom',\n", " 'GEM2_BOARD_INTERFACE': 'custom',\n", " 'GEM3_BOARD_INTERFACE': 'custom',\n", " 'GPIO_BOARD_INTERFACE': 'custom',\n", " 'HAS_BRESP': '1',\n", " 'HAS_BURST': '1',\n", " 'HAS_CACHE': '1',\n", " 'HAS_LOCK': '1',\n", " 'HAS_PROT': '1',\n", " 'HAS_QOS': '1',\n", " 'HAS_REGION': '0',\n", " 'HAS_RRESP': '1',\n", " 'HAS_WSTRB': '1',\n", " 'ID_WIDTH': '16',\n", " 'IIC0_BOARD_INTERFACE': 'custom',\n", " 'IIC1_BOARD_INTERFACE': 'custom',\n", " 'INSERT_VIP': '0',\n", " 'MAX_BURST_LENGTH': '256',\n", " 'NAND_BOARD_INTERFACE': 'custom',\n", " 'NUM_READ_OUTSTANDING': '8',\n", " 'NUM_READ_THREADS': '4',\n", " 'NUM_WRITE_OUTSTANDING': '8',\n", " 'NUM_WRITE_THREADS': '4',\n", " 'PCIE_BOARD_INTERFACE': 'custom',\n", " 'PHASE': '0.0',\n", " 'PJTAG_BOARD_INTERFACE': 'custom',\n", " 'PMU_BOARD_INTERFACE': 'custom',\n", " 'PROTOCOL': 'AXI4',\n", " 'PSU_BANK_0_IO_STANDARD': 'LVCMOS33',\n", " 'PSU_BANK_1_IO_STANDARD': 'LVCMOS18',\n", " 'PSU_BANK_2_IO_STANDARD': 'LVCMOS18',\n", " 'PSU_BANK_3_IO_STANDARD': 'LVCMOS18',\n", " 'PSU_DDR_RAM_HIGHADDR': '0xFFFFFFFF',\n", " 'PSU_DDR_RAM_HIGHADDR_OFFSET': '0x800000000',\n", " 'PSU_DDR_RAM_LOWADDR_OFFSET': '0x80000000',\n", " 'PSU_DYNAMIC_DDR_CONFIG_EN': '0',\n", " 'PSU_IMPORT_BOARD_PRESET': None,\n", " 'PSU_MIO_0_DIRECTION': 'inout',\n", " 'PSU_MIO_0_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_0_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_0_POLARITY': 'Default',\n", " 'PSU_MIO_0_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_0_SLEW': 'fast',\n", " 'PSU_MIO_10_DIRECTION': 'inout',\n", " 'PSU_MIO_10_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_10_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_10_POLARITY': 'Default',\n", " 'PSU_MIO_10_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_10_SLEW': 'fast',\n", " 'PSU_MIO_11_DIRECTION': 'inout',\n", " 'PSU_MIO_11_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_11_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_11_POLARITY': 'Default',\n", " 'PSU_MIO_11_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_11_SLEW': 'fast',\n", " 'PSU_MIO_12_DIRECTION': '',\n", " 'PSU_MIO_17_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_17_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_17_POLARITY': 'Default',\n", " 'PSU_MIO_17_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_17_SLEW': 'fast',\n", " 'PSU_MIO_18_DIRECTION': 'inout',\n", " 'PSU_MIO_18_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_18_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_18_POLARITY': 'Default',\n", " 'PSU_MIO_18_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_18_SLEW': 'fast',\n", " 'PSU_MIO_19_DIRECTION': 'inout',\n", " 'PSU_MIO_19_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_19_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_19_POLARITY': 'Default',\n", " 'PSU_MIO_19_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_19_SLEW': 'fast',\n", " 'PSU_MIO_1_DIRECTION': 'out',\n", " 'PSU_MIO_1_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_1_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_1_POLARITY': 'Default',\n", " 'PSU_MIO_1_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_1_SLEW': 'fast',\n", " 'PSU_MIO_20_DIRECTION': '',\n", " 'PSU_MIO_23_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_23_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_23_POLARITY': 'Default',\n", " 'PSU_MIO_23_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_23_SLEW': 'fast',\n", " 'PSU_MIO_24_DIRECTION': 'in',\n", " 'PSU_MIO_24_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_24_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_24_POLARITY': 'Default',\n", " 'PSU_MIO_24_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_24_SLEW': 'fast',\n", " 'PSU_MIO_25_DIRECTION': 'in',\n", " 'PSU_MIO_25_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_25_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_25_POLARITY': 'Default',\n", " 'PSU_MIO_25_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_25_SLEW': 'fast',\n", " 'PSU_MIO_26_DIRECTION': '',\n", " 'PSU_MIO_31_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_31_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_31_POLARITY': 'Default',\n", " 'PSU_MIO_31_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_31_SLEW': 'fast',\n", " 'PSU_MIO_32_DIRECTION': 'out',\n", " 'PSU_MIO_32_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_32_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_32_POLARITY': 'Default',\n", " 'PSU_MIO_32_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_32_SLEW': 'fast',\n", " 'PSU_MIO_33_DIRECTION': 'in',\n", " 'PSU_MIO_33_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_33_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_33_POLARITY': 'Default',\n", " 'PSU_MIO_33_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_33_SLEW': 'fast',\n", " 'PSU_MIO_34_DIRECTION': '',\n", " 'PSU_MIO_35_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_35_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_35_POLARITY': 'Default',\n", " 'PSU_MIO_35_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_35_SLEW': 'fast',\n", " 'PSU_MIO_36_DIRECTION': 'inout',\n", " 'PSU_MIO_36_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_36_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_36_POLARITY': 'Default',\n", " 'PSU_MIO_36_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_36_SLEW': 'fast',\n", " 'PSU_MIO_37_DIRECTION': 'inout',\n", " 'PSU_MIO_37_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_37_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_37_POLARITY': 'Default',\n", " 'PSU_MIO_37_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_37_SLEW': 'fast',\n", " 'PSU_MIO_38_DIRECTION': 'out',\n", " 'PSU_MIO_38_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_38_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_38_POLARITY': 'Default',\n", " 'PSU_MIO_38_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_38_SLEW': 'fast',\n", " 'PSU_MIO_39_DIRECTION': 'out',\n", " 'PSU_MIO_39_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_39_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_39_POLARITY': 'Default',\n", " 'PSU_MIO_39_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_39_SLEW': 'fast',\n", " 'PSU_MIO_3_DIRECTION': 'inout',\n", " 'PSU_MIO_3_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_3_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_3_POLARITY': 'Default',\n", " 'PSU_MIO_3_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_3_SLEW': 'fast',\n", " 'PSU_MIO_40_DIRECTION': 'out',\n", " 'PSU_MIO_40_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_40_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_40_POLARITY': 'Default',\n", " 'PSU_MIO_40_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_40_SLEW': 'fast',\n", " 'PSU_MIO_41_DIRECTION': 'out',\n", " 'PSU_MIO_41_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_41_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_41_POLARITY': 'Default',\n", " 'PSU_MIO_41_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_41_SLEW': 'fast',\n", " 'PSU_MIO_42_DIRECTION': 'out',\n", " 'PSU_MIO_42_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_42_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_42_POLARITY': 'Default',\n", " 'PSU_MIO_42_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_42_SLEW': 'fast',\n", " 'PSU_MIO_43_DIRECTION': 'out',\n", " 'PSU_MIO_43_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_43_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_43_POLARITY': 'Default',\n", " 'PSU_MIO_43_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_43_SLEW': 'fast',\n", " 'PSU_MIO_44_DIRECTION': 'in',\n", " 'PSU_MIO_44_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_44_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_44_POLARITY': 'Default',\n", " 'PSU_MIO_44_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_44_SLEW': 'fast',\n", " 'PSU_MIO_45_DIRECTION': 'in',\n", " 'PSU_MIO_45_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_45_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_45_POLARITY': 'Default',\n", " 'PSU_MIO_45_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_45_SLEW': 'fast',\n", " 'PSU_MIO_46_DIRECTION': 'in',\n", " 'PSU_MIO_46_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_46_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_46_POLARITY': 'Default',\n", " 'PSU_MIO_46_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_46_SLEW': 'fast',\n", " 'PSU_MIO_47_DIRECTION': 'in',\n", " 'PSU_MIO_47_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_47_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_47_POLARITY': 'Default',\n", " 'PSU_MIO_47_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_47_SLEW': 'fast',\n", " 'PSU_MIO_48_DIRECTION': 'in',\n", " 'PSU_MIO_48_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_48_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_48_POLARITY': 'Default',\n", " 'PSU_MIO_48_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_48_SLEW': 'fast',\n", " 'PSU_MIO_49_DIRECTION': 'in',\n", " 'PSU_MIO_49_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_49_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_49_POLARITY': 'Default',\n", " 'PSU_MIO_49_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_49_SLEW': 'fast',\n", " 'PSU_MIO_4_DIRECTION': 'inout',\n", " 'PSU_MIO_4_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_4_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_4_POLARITY': 'Default',\n", " 'PSU_MIO_4_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_4_SLEW': 'fast',\n", " 'PSU_MIO_50_DIRECTION': 'out',\n", " 'PSU_MIO_50_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_50_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_50_POLARITY': 'Default',\n", " 'PSU_MIO_50_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_50_SLEW': 'fast',\n", " 'PSU_MIO_51_DIRECTION': 'inout',\n", " 'PSU_MIO_51_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_51_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_51_POLARITY': 'Default',\n", " 'PSU_MIO_51_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_51_SLEW': 'fast',\n", " 'PSU_MIO_52_DIRECTION': 'in',\n", " 'PSU_MIO_52_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_52_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_52_POLARITY': 'Default',\n", " 'PSU_MIO_52_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_52_SLEW': 'fast',\n", " 'PSU_MIO_53_DIRECTION': 'in',\n", " 'PSU_MIO_53_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_53_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_53_POLARITY': 'Default',\n", " 'PSU_MIO_53_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_53_SLEW': 'fast',\n", " 'PSU_MIO_54_DIRECTION': 'inout',\n", " 'PSU_MIO_54_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_54_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_54_POLARITY': 'Default',\n", " 'PSU_MIO_54_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_54_SLEW': 'fast',\n", " 'PSU_MIO_55_DIRECTION': 'in',\n", " 'PSU_MIO_55_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_55_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_55_POLARITY': 'Default',\n", " 'PSU_MIO_55_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_55_SLEW': 'fast',\n", " 'PSU_MIO_56_DIRECTION': 'inout',\n", " 'PSU_MIO_56_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_56_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_56_POLARITY': 'Default',\n", " 'PSU_MIO_56_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_56_SLEW': 'fast',\n", " 'PSU_MIO_57_DIRECTION': 'inout',\n", " 'PSU_MIO_57_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_57_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_57_POLARITY': 'Default',\n", " 'PSU_MIO_57_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_57_SLEW': 'fast',\n", " 'PSU_MIO_58_DIRECTION': 'out',\n", " 'PSU_MIO_58_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_58_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_58_POLARITY': 'Default',\n", " 'PSU_MIO_58_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_58_SLEW': 'fast',\n", " 'PSU_MIO_59_DIRECTION': 'inout',\n", " 'PSU_MIO_59_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_59_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_59_POLARITY': 'Default',\n", " 'PSU_MIO_59_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_59_SLEW': 'fast',\n", " 'PSU_MIO_5_DIRECTION': 'inout',\n", " 'PSU_MIO_5_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_5_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_5_POLARITY': 'Default',\n", " 'PSU_MIO_5_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_5_SLEW': 'fast',\n", " 'PSU_MIO_60_DIRECTION': 'inout',\n", " 'PSU_MIO_60_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_60_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_60_POLARITY': 'Default',\n", " 'PSU_MIO_60_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_60_SLEW': 'fast',\n", " 'PSU_MIO_61_DIRECTION': 'inout',\n", " 'PSU_MIO_61_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_61_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_61_POLARITY': 'Default',\n", " 'PSU_MIO_61_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_61_SLEW': 'fast',\n", " 'PSU_MIO_62_DIRECTION': 'inout',\n", " 'PSU_MIO_62_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_62_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_62_POLARITY': 'Default',\n", " 'PSU_MIO_62_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_62_SLEW': 'fast',\n", " 'PSU_MIO_63_DIRECTION': 'inout',\n", " 'PSU_MIO_63_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_63_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_63_POLARITY': 'Default',\n", " 'PSU_MIO_63_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_63_SLEW': 'fast',\n", " 'PSU_MIO_64_DIRECTION': 'in',\n", " 'PSU_MIO_64_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_64_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_64_POLARITY': 'Default',\n", " 'PSU_MIO_64_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_64_SLEW': 'fast',\n", " 'PSU_MIO_65_DIRECTION': 'in',\n", " 'PSU_MIO_65_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_65_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_65_POLARITY': 'Default',\n", " 'PSU_MIO_65_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_65_SLEW': 'fast',\n", " 'PSU_MIO_66_DIRECTION': 'inout',\n", " 'PSU_MIO_66_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_66_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_66_POLARITY': 'Default',\n", " 'PSU_MIO_66_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_66_SLEW': 'fast',\n", " 'PSU_MIO_67_DIRECTION': 'in',\n", " 'PSU_MIO_67_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_67_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_67_POLARITY': 'Default',\n", " 'PSU_MIO_67_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_67_SLEW': 'fast',\n", " 'PSU_MIO_68_DIRECTION': 'inout',\n", " 'PSU_MIO_68_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_68_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_68_POLARITY': 'Default',\n", " 'PSU_MIO_68_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_68_SLEW': 'fast',\n", " 'PSU_MIO_69_DIRECTION': 'inout',\n", " 'PSU_MIO_69_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_69_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_69_POLARITY': 'Default',\n", " 'PSU_MIO_69_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_69_SLEW': 'fast',\n", " 'PSU_MIO_6_DIRECTION': 'inout',\n", " 'PSU_MIO_6_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_6_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_6_POLARITY': 'Default',\n", " 'PSU_MIO_6_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_6_SLEW': 'fast',\n", " 'PSU_MIO_70_DIRECTION': 'out',\n", " 'PSU_MIO_70_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_70_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_70_POLARITY': 'Default',\n", " 'PSU_MIO_70_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_70_SLEW': 'fast',\n", " 'PSU_MIO_71_DIRECTION': 'inout',\n", " 'PSU_MIO_71_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_71_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_71_POLARITY': 'Default',\n", " 'PSU_MIO_71_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_71_SLEW': 'fast',\n", " 'PSU_MIO_72_DIRECTION': 'inout',\n", " 'PSU_MIO_72_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_72_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_72_POLARITY': 'Default',\n", " 'PSU_MIO_72_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_72_SLEW': 'fast',\n", " 'PSU_MIO_73_DIRECTION': 'inout',\n", " 'PSU_MIO_73_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_73_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_73_POLARITY': 'Default',\n", " 'PSU_MIO_73_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_73_SLEW': 'fast',\n", " 'PSU_MIO_74_DIRECTION': 'inout',\n", " 'PSU_MIO_74_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_74_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_74_POLARITY': 'Default',\n", " 'PSU_MIO_74_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_74_SLEW': 'fast',\n", " 'PSU_MIO_75_DIRECTION': 'inout',\n", " 'PSU_MIO_75_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_75_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_75_POLARITY': 'Default',\n", " 'PSU_MIO_75_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_75_SLEW': 'fast',\n", " 'PSU_MIO_76_DIRECTION': '',\n", " 'PSU_MIO_77_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_77_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_77_POLARITY': 'Default',\n", " 'PSU_MIO_77_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_77_SLEW': 'fast',\n", " 'PSU_MIO_7_DIRECTION': '',\n", " 'PSU_MIO_8_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_8_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_8_POLARITY': 'Default',\n", " 'PSU_MIO_8_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_8_SLEW': 'fast',\n", " 'PSU_MIO_9_DIRECTION': 'inout',\n", " 'PSU_MIO_9_DRIVE_STRENGTH': '12',\n", " 'PSU_MIO_9_INPUT_TYPE': 'cmos',\n", " 'PSU_MIO_9_POLARITY': 'Default',\n", " 'PSU_MIO_9_PULLUPDOWN': 'pullup',\n", " 'PSU_MIO_9_SLEW': 'fast',\n", " 'PSU_MIO_TREE_PERIPHERALS': 'SPI 0#SPI '\n", " '0#SPI 0#SPI '\n", " '0#SPI 0#SPI '\n", " '0#SPI '\n", " '1###SPI '\n", " '1#SPI 1#SPI '\n", " '1##SD 0#SD '\n", " '0#SD 0#SD '\n", " '0##I2C '\n", " '0#I2C 0##SD '\n", " '0#SD 0##SD '\n", " '0#SD '\n", " '0##DPAUX#DPAUX#DPAUX#DPAUX##UART '\n", " '1#UART '\n", " '1###I2C '\n", " '1#I2C 1#Gem '\n", " '1#Gem 1#Gem '\n", " '1#Gem 1#Gem '\n", " '1#Gem 1#Gem '\n", " '1#Gem 1#Gem '\n", " '1#Gem 1#Gem '\n", " '1#Gem '\n", " '1#MDIO '\n", " '1#MDIO '\n", " '1#USB 0#USB '\n", " '0#USB 0#USB '\n", " '0#USB 0#USB '\n", " '0#USB 0#USB '\n", " '0#USB 0#USB '\n", " '0#USB 0#USB '\n", " '0#USB 1#USB '\n", " '1#USB 1#USB '\n", " '1#USB 1#USB '\n", " '1#USB 1#USB '\n", " '1#USB 1#USB '\n", " '1#USB 1#USB '\n", " '1##',\n", " 'PSU_MIO_TREE_SIGNALS': 'sclk_out#n_ss_out[2]#n_ss_out[1]#n_ss_out[0]#miso#mosi#sclk_out###n_ss_out[0]#miso#mosi##sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]##scl_out#sda_out##sdio0_cmd_out#sdio0_clk_out##sdio0_cd_n#sdio0_wp##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in##txd#rxd###scl_out#sda_out#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem1_mdc#gem1_mdio_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]##',\n", " 'PSU_PERIPHERAL_BOARD_PRESET': None,\n", " 'PSU_SD0_INTERNAL_BUS_WIDTH': '4',\n", " 'PSU_SD1_INTERNAL_BUS_WIDTH': '8',\n", " 'PSU_SMC_CYCLE_T0': 'NA',\n", " 'PSU_SMC_CYCLE_T1': 'NA',\n", " 'PSU_SMC_CYCLE_T2': 'NA',\n", " 'PSU_SMC_CYCLE_T3': 'NA',\n", " 'PSU_SMC_CYCLE_T4': 'NA',\n", " 'PSU_SMC_CYCLE_T5': 'NA',\n", " 'PSU_SMC_CYCLE_T6': 'NA',\n", " 'PSU_UIPARAM_GENERATE_SUMMARY': '',\n", " 'PSU__CAN0__PERIPHERAL__ENABLE': '0',\n", " 'PSU__CAN0__PERIPHERAL__IO': '',\n", " 'PSU__CAN1__PERIPHERAL__ENABLE': '0',\n", " 'PSU__CAN1__PERIPHERAL__IO': '',\n", " 'PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ': '249.999954',\n", " 'PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ': '250',\n", " 'PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ': '125',\n", " 'PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0': '5',\n", " 'PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ': '250',\n", " 'PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ': '249.999954',\n", " 'PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ': '250',\n", " 'PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ': '599.999878',\n", " 'PSU__CRF_APB__DDR_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__DDR_CTRL__FREQMHZ': '1200',\n", " 'PSU__CRF_APB__DDR_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ': '599.999878',\n", " 'PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ': '600',\n", " 'PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__DPLL_CTRL__DIV2': '1',\n", " 'PSU__CRF_APB__DPLL_CTRL__FBDIV': '72',\n", " 'PSU__CRF_APB__DPLL_CTRL__FRACDATA': '0.000000',\n", " 'PSU__CRF_APB__DPLL_CTRL__FRACFREQ': '27.138',\n", " 'PSU__CRF_APB__DPLL_CTRL__SRCSEL': 'PSS_REF_CLK',\n", " 'PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED': '0',\n", " 'PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0': '3',\n", " 'PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ': '24.999996',\n", " 'PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0': '21',\n", " 'PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1': '1',\n", " 'PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ': '25',\n", " 'PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL': 'RPLL',\n", " 'PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED': '0',\n", " 'PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ': '26.249996',\n", " 'PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0': '20',\n", " 'PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1': '1',\n", " 'PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ': '27',\n", " 'PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL': 'RPLL',\n", " 'PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ': '299.999939',\n", " 'PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0': '4',\n", " 'PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1': '1',\n", " 'PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ': '300',\n", " 'PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED': '0',\n", " 'PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ': '599.999878',\n", " 'PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ': '600',\n", " 'PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ': '0',\n", " 'PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0': '3',\n", " 'PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ': '600',\n", " 'PSU__CRF_APB__GPU_REF_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ': '-1',\n", " 'PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0': '-1',\n", " 'PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ': '-1',\n", " 'PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL': 'NA',\n", " 'PSU__CRF_APB__GTGREF0__ENABLE': 'NA',\n", " 'PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ': '250',\n", " 'PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0': '6',\n", " 'PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ': '250',\n", " 'PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ': '250',\n", " 'PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0': '5',\n", " 'PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ': '250',\n", " 'PSU__CRF_APB__SATA_REF_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ': '99.999985',\n", " 'PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0': '5',\n", " 'PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ': '100',\n", " 'PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ': '399.999908',\n", " 'PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0': '3',\n", " 'PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ': '533.33',\n", " 'PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL': 'DPLL',\n", " 'PSU__CRF_APB__VPLL_CTRL__DIV2': '1',\n", " 'PSU__CRF_APB__VPLL_CTRL__FBDIV': '90',\n", " 'PSU__CRF_APB__VPLL_CTRL__FRACDATA': '0.000000',\n", " 'PSU__CRF_APB__VPLL_CTRL__FRACFREQ': '27.138',\n", " 'PSU__CRF_APB__VPLL_CTRL__SRCSEL': 'PSS_REF_CLK',\n", " 'PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED': '0',\n", " 'PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0': '4',\n", " 'PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ': '524.999939',\n", " 'PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0': '2',\n", " 'PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ': '533.333',\n", " 'PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL': 'RPLL',\n", " 'PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ': '500',\n", " 'PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0': '3',\n", " 'PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ': '500',\n", " 'PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRL_APB__AFI6__ENABLE': '0',\n", " 'PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ': '49.999992',\n", " 'PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0': '30',\n", " 'PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1': '1',\n", " 'PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ': '50',\n", " 'PSU__CRL_APB__AMS_REF_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ': '100',\n", " 'PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0': '15',\n", " 'PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1': '1',\n", " 'PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ': '100',\n", " 'PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL': 'IOPLL',\n", " 'PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ': '100',\n", " 'PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0': '15',\n", " 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